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LPC4350 Datasheet(PDF) 89 Page - NXP Semiconductors |
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LPC4350 Datasheet(HTML) 89 Page - NXP Semiconductors |
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89 / 145 page ![]() LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 2.1 — 23 September 2011 89 of 145 NXP Semiconductors LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller 8. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] 2.0 V if VBAT 2.2 V. [3] Including voltage on outputs in 3-state mode; at 2.0 V the speed will be reduced. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDD_REG 2.2[2] 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 2.2 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 2.0 3.6 V VBAT battery supply voltage for the RTC 2.2 3.6 V Vprog(pf) polyfuse programming voltage on pin VPP 2.7 3.6 V VI input voltage only valid when the VDD(IO) supply voltage is present 5 V tolerant I/O pins (see Table 3) [3] 0.5 5.5 V ADC/DAC pins and digital I/O pins configured for an analog function (see Table 3) <tbd> VDDA(3V3) V USB1 pins USB1_DP and USB1_DM (see Table 3) <tbd> <tbd> V IDD supply current per supply pin [4] - <tbd> mA ISS ground current per ground pin [4] - <tbd> mA Ilatch I/O latch-up current (0.5V DD(IO)) < VI < (1.5VDD(IO)); Tj < 125 C - <tbd> mA Tstg storage temperature [5] <tbd> <tbd> C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - <tbd> W VESD electrostatic discharge voltage human body model; all pins [6] <tbd> <tbd> V |
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