LPC4350 datasheet(68/145 Pages) NXP

68 / 145 page

LPC4350_30_20_10

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2.1 — 23 September 2011

68 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

7.11 In-System Programming (ISP)

In-System programming (ISP) is programming or reprogramming the on-chip SRAM

memory, using the boot loader software and the USART0 serial port. This can be done

when the part resides in the end-user board. ISP allows to load data into on-chip SRAM

and execute code from on-chip SRAM.

7.12 Boot ROM

The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After

a reset, the ARM processor will start its code execution from this memory.

The boot ROM memory includes the following features:

• ROM memory size is 64 kB.

• Supports booting from UART interfaces and external static memory such as NOR

flash, SPI flash, quad SPI flash.

• Includes APIs for power control and OTP programming.

• Includes SPIFI drivers.

• Includes a flexible USB device stack that supports Human Interface Device (HID),

Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.

AES capable parts also support:

• CMAC authentication on the boot image.

• Secure booting from an encrypted image. In development mode booting from a plain

text image is possible. Development mode is terminated by programming the AES

key.

• API for AES programming.

Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If

the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is

determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.

Table 4.

Boot mode when OTP BOOT_SRC bits are programmed

Boot mode BOOT_SRC

bit 3

BOOT_SRC

bit 2

BOOT_SRC

bit 1

BOOT_SRC

bit 0

Description

Pin state

Boot source is defined by the reset state of P1_1,

P1_2, P2_8 pins, and P2_9. See Table 5.

UART

Boot from device connected to USART0 using pins

P2_0 and P2_1.

SPIFI

Boot from Quad SPI flash connected to the SPIFI

interface using pins P3_3 to P3_8.

EMC 8-bit

Boot from external static memory (such as NOR

flash) using CS0 and an 8-bit data bus.

EMC 16-bit

Boot from external static memory (such as NOR

flash) using CS0 and a 16-bit data bus.

EMC 32-bit

Boot from external static memory (such as NOR

flash) using CS0 and a 32-bit data bus.

USB0

011

0Boot from USB0.

LPC4350 Datasheet(PDF) 68 Page - NXP Semiconductors

LPC4350 Datasheet(HTML) 68 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL