4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and

28-Port I/O Expander

10

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Table 3. Register Address Map

COMMAND ADDRESS

REGISTER

D15

D14

D13

D12

D11

D10

D9

D8

HEX

CODE

No-Op

R/

W

00

00

0

0

0

0x00

Configuration

R/

W

00

00

1

0

0

0x04

Transition Detect Mask

R/

W

00

00

1

1

0

0x06

Factory Reserved. Do not write to this.

R/

W

00

00

1

1

1

0x07

Port Configuration P7, P6, P5, P4

R/

W

00

01

0

0

1

0x09

Port Configuration P11, P10, P9, P8

R/

W

00

01

0

1

0

0x0A

Port Configuration P15, P14, P13, P12

R/

W

00

01

0

1

1

0x0B

Port Configuration P19, P18, P17, P16

R/

W

00

01

1

0

0

0x0C

Port Configuration P23, P22, P21, P20

R/

W

00

01

1

0

1

0x0D

Port Configuration P27, P26, P25, P24

R/

W

00

01

1

1

0

0x0E

Port Configuration P31, P30, P29, P28

R/

W

00

01

1

1

1

0x0F

Port 0 only (virtual port, no action)

R/

W

01

00

0

0

0

0x20

Port 1 only (virtual port, no action)

R/

W

01

00

0

0

1

0x21

Port 2 only (virtual port, no action)

R/

W

01

00

0

1

0

0x22

Port 3 only (virtual port, no action)

R/

W

01

00

0

1

1

0x23

Port 4 only (data bit D0. D7–D1 read as 0)

R/

W

01

00

1

0

0

0x24

Port 5 only (data bit D0. D7–D1 read as 0)

R/

W

01

00

1

0

1

0x25

Port 6 only (data bit D0. D7–D1 read as 0)

R/

W

01

00

1

1

0

0x26

Port 7 only (data bit D0. D7–D1 read as 0)

R/

W

01

00

1

1

1

0x27

Port 8 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

0

0

0

0x28

Port 9 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

0

0

1

0x29

Port 10 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

0

1

0

0x2A

Port 11 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

0

1

1

0x2B

Port 12 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

1

0

0

0x2C

Port 13 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

1

0

1

0x2D

Port 14 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

1

1

0

0x2E

Port 15 only (data bit D0. D7–D1 read as 0)

R/

W

01

01

1

1

1

0x2F

Port 16 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

0

0

0

0x30

Port 17 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

0

0

1

0x31

Port 18 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

0

1

0

0x32

Port 19 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

0

1

1

0x33

Port 20 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

1

0

0

0x34

Port 21 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

1

0

1

0x35

Port 22 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

1

1

0

0x36

Port 23 only (data bit D0. D7–D1 read as 0)

R/

W

01

10

1

1

1

0x37

Port 24 only (data bit D0. D7–D1 read as 0)

R/

W

01

11

0

0

0

0x38

Port 25 only (data bit D0. D7–D1 read as 0)

R/

W

01

11

0

0

1

0x39