MAXQ2000-RFX+ datasheet(13/39 Pages) MAXIM

13 / 39 page

Low-Power LCD Microcontroller

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Detailed Description

The following is an introduction to the primary features

of the microcontroller. More detailed descriptions of the

device features can be found in the data sheets, errata

sheets, and user’s guides described later in the

Additional Documentation section.

MAXQ Core Architecture

The MAXQ2000 is a low-cost, high-performance,

CMOS, fully static, 16-bit RISC microcontroller with flash

memory and an integrated 100- or 132-segment LCD

controller. It is structured on a highly advanced, accu-

mulator-based, 16-bit RISC architecture. Fetch and exe-

cution operations are completed in one cycle without

pipelining, because the instruction contains both the op

code and data. The result is a streamlined 20 million

instructions-per-second (MIPS) microcontroller.

The highly efficient core is supported by a 16-level

hardware stack, enabling fast subroutine calling and

task switching. Data can be quickly and efficiently

manipulated with three internal data pointers. Multiple

data pointers allow more than one function to access

data memory without having to save and restore data

pointers each time. The data pointers can automatically

increment or decrement following an operation, elimi-

nating the need for software intervention. As a result,

application speed is greatly increased.

Instruction Set

The instruction set is composed of fixed-length, 16-bit

instructions that operate on registers and memory loca-

tions. The instruction set is highly orthogonal, allowing

arithmetic and logical operations to use any register

along with the accumulator. Special-function registers

control the peripherals and are subdivided into register

modules. The family architecture is modular, so that

new devices and modules can reuse code developed

for existing products.

The architecture is transport-triggered. This means that

writes or reads from certain register locations can also

cause side effects to occur. These side effects form the

basis for the higher-level op codes defined by the

assembler, such as ADDC, OR, JUMP, etc. The op

codes are actually implemented as MOVE instructions

between certain register locations, while the assembler

handles the encoding, which need not be a concern to

the programmer.

The 16-bit instruction word is designed for efficient exe-

cution. Bit 15 indicates the format for the source field of

the instruction. Bits 0 to 7 of the instruction represent the

source for the transfer. Depending on the value of the

format field, this can either be an immediate value or a

source register. If this field represents a register, the

lower four bits contain the module specifier and the

upper four bits contain the register index in that module.

Bits 8 to 14 represent the destination for the transfer.

This value always represents a destination register, with

the lower four bits containing the module specifier and

the upper three bits containing the register subindex

within that module. Any time that it is necessary to

directly select one of the upper 24 registers as a desti-

nation, the prefix register, PFX, is needed to supply the

extra destination bits. This prefix register write is insert-

ed automatically by the assembler and requires only

one additional execution cycle.

Memory Organization

The device incorporates several memory areas:

• 4kB utility ROM,

• 32kWords of flash memory for program storage,

• 1kWord of SRAM for storage of temporary variables, and

• 16-level stack memory for storage of program return

addresses and general-purpose use.

The memory is arranged by default in a Harvard archi-

tecture, with separate address spaces for program and

data memory. A special mode allows data memory to be

mapped into program space, permitting code execution

from data memory. In addition, another mode allows pro-

gram memory to be mapped into data space, permitting

code constants to be accessed as data memory.

The incorporation of flash memory allows the devices to

be reprogrammed, eliminating the expense of throwing

away one-time programmable devices during develop-

ment and field upgrades. Flash memory can be pass-

word protected with a 16-word key, denying access to

program memory by unauthorized individuals.

A pseudo-Von Neumann memory map can also be

enabled. This places the utility ROM, code, and data

memory into a single contiguous memory map. This is

useful for applications that require dynamic program

modification or unique memory configurations.

Stack Memory

A 16-bit-wide internal stack provides storage for pro-

gram return addresses and general-purpose use. The

stack is used automatically by the processor when the

CALL, RET, and RETI instructions are executed and

interrupts serviced. The stack can also be used explic-

itly to store and retrieve data by using the PUSH, POP,

and POPI instructions.

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