MAXQ2000-RFX+ datasheet(27/39 Pages) MAXIM

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Low-Power LCD Microcontroller

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Power Management

Advanced power-management features minimize

power consumption by dynamically matching the pro-

cessing speed of the device to the required perfor-

mance level. This means device operation can be

slowed and power consumption minimized during peri-

ods of reduced activity. When more processing power

is required, the microcontroller can increase its operat-

ing frequency. Software-selectable clock-divide opera-

tions allow flexibility, selecting whether a system clock

cycle is 1, 2, 4, or 8 oscillator cycles. By performing this

function in software, a lower power state can be

entered without the cost of additional hardware.

For extremely power-sensitive applications, three addi-

tional low-power modes are available:

• PMM1: divide-by-256 power-management mode

(PMME = 1, CD1:0 = 00b)

• PMM2: 32kHz power-management mode (PMME = 1,

CD1:0 = 11b)

• Stop mode (STOP = 1)

In PMM1, one system clock is 256 oscillator cycles, sig-

nificantly reducing power consumption while the micro-

controller functions at reduced speed. In PMM2, the

device can run even slower by using the 32kHz oscilla-

tor as the clock source. The optional switchback fea-

ture allows enabled interrupt sources including external

interrupts, UARTs, and the SPI module to quickly exit

the power-management modes and return to a faster

internal clock rate.

Power consumption reaches its minimum in Stop mode.

In this mode, the external oscillator, system clock, and all

processing activity is halted. Stop mode is exited when

an enabled external interrupt pin is triggered, an external

reset signal is applied to the RESET pin, or the RTC time-

of-day alarm is activated. Upon exiting Stop mode, the

microcontroller can choose to wait for the external high-

frequency crystal to complete its warmup period, or it

can start execution immediately from its internal ring

oscillator while the warmup period completes.

Interrupts

Multiple interrupt sources are available for quick

response to internal and external events. The MAXQ

architecture uses a single interrupt vector (IV), single

interrupt-service routine (ISR) design. For maximum

flexibility, interrupts can be enabled globally, individual-

ly, or by module. When an interrupt condition occurs,

its individual flag is set, even if the interrupt source is

disabled at the local, module, or global level. Interrupt

flags must be cleared within the user-interrupt routine

to avoid repeated interrupts from the same source.

Application software must ensure a delay between the

write to the flag and the RETI instruction to allow time

for the interrupt hardware to remove the internal inter-

rupt condition. Asynchronous interrupt flags require a

one-instruction delay and synchronous interrupt flags

require a two-instruction delay.

When an enabled interrupt is detected, software jumps

to a user-programmable interrupt vector location. The

IV register defaults to 0000h on reset or power-up, so if

it is not changed to a different address, the user pro-

gram must determine whether a jump to 0000h came

from a reset or interrupt source.

Once software control has been transferred to the ISR,

the interrupt identification register (IIR) can be used to

determine if a system register or peripheral register

was the source of the interrupt. The specified module

can then be interrogated for the specific interrupt

source and software can take appropriate action.

Because the interrupts are evaluated by user software,

the user can define a unique interrupt priority scheme

for each application. The following interrupt sources are

available. Sources marked with an asterisk are not

available on the 56-pin version.

• Watchdog Interrupt

• External Interrupts 0 to 15 (INT10*, INT11*)

• RTC Time-of-Day and Subsecond Alarms

• Serial Port 0 Receive and Transmit Interrupts

• Serial Port 1 Receive and Transmit Interrupts*

• SPI Mode Fault, Write Collision, Receive Overrun, and

Transfer Complete Interrupts

• Timer 0 Low Compare, Low Overflow,

Capture/Compare, and Overflow Interrupts

• Timer 1 Low Compare, Low Overflow,

Capture/Compare, and Overflow Interrupts

• Timer 2 Low Compare, Low Overflow,

Capture/Compare, and Overflow Interrupts

• 1-Wire Presence Detect, Transmit Buffer Empty,

Transmit Shift Register Empty, Receive Buffer Full,

and Shift Register Full, Short, and Low Interrupts*

Reset Sources

Several reset sources are provided for microcontroller

control. Although code execution is halted in the reset

state, the high-frequency oscillator and the ring oscillator

continue to oscillate. Internal resets such as the power-

on and watchdog resets assert the RESET pin low.

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