TPS40400 datasheet(17/72 Pages) TI

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(

)

LIN

BP6

VDD

GATE

(

)

GATE

gHIGH

gLOW

exp onent

Value

Mantissa

TPS40400

www.ti.com

SLUS930B

– APRIL 2011 – REVISED OCTOBER 2011

Current limits must also be observed. Shorting the BP3 pin to GND damages the BP3 regulator. The BP3

regulator input comes from the BP6 regulator output. The current limit circuit on the BP6 regulator is 100 mA so

the total current drawn from both regulators must be less than that. This total current includes the TPS40400

operating current IVDD plus the gate drive current required to drive the power FETs. The total available current

from two regulators is found in Equation 3 and Equation 4:

(3)

where

•

ILIN is the total current that can be drawn from BP3 and BP6 in aggregate

•

IBP6 is the current limit of the BP6 regulator – 100 mA minimum

•

IVDD is the quiescent current of the TPS40400 – 15 mA maximum

•

IGATE is the gate drive current required by the power FETs

•

fSW is the switching frequency

•

QgHIGH is the total gate charge required by the high-side FET

•

QgLOW is the total gate charge required by the low-side FET

(4)

PMBus address. The PMBus specification requires that each device connected to the PMBus have a unique

address on the bus. The TPS40400 has 64 possible addresses (0 through 63 in decimal) that can be assigned

by connecting resistors from the ADDR0 and ADDR1 pins to SGND. The address is set in the form of two octal

(0-7) digits, one digit for each pin. ADDR1 is the high-order digit and ADDR0 is the low-order digit.

The E96 series resistors suggested for each digit value are shown in Table 1.

Table 1. E96 Series Resistors

DIGIT

RESISTANCE (k

Ω)

15.4

23.7

36.5

54.9

84.5

130

200

The TPS40400 also detects values that are out of range on the ADDR0 and ADDR1 pins. If either pin is detected

as having an out of range resistance connected to it, the TPS40400 continues to respond to PMBus commands,

but at address 127, which is outside of the possible programmed addresses. It is possible but not recommended

to use the device in this condition, especially if other TPS40400 devices are present on the bus or if another

device could possibly occupy the 127 address.

PMBus connections. The TPS40400 supports both the 100 kHz and 400 kHz bus speeds. Connection for the

PMBus interface should follow the High Power DC specifications given in section 3.1.3 in the SMBus

specification V2.0 for the 400-kHz bus speed or the Low Power DC specifications in section 3.1.2. The complete

SMBus specification is available from the SMBus web site, smbus.org.

PMBus Functionality and Additional Setup

Data format.There are three data formats supported in PMBus form commands that require representation of a

literal number as their argument (commands that set thresholds, voltages or report such). A compatible device

needs to only support one of these formats. The TPS40400 supports the Linear data format only for these

commands. In this format, the data argument consists of two parts, a mantissa and an exponent. The number

represented by this argument can be expressed as shown in Equation 5.

(5)

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