IC-DC datasheet(16/19 Pages) ICHAUS

16 / 19 page

preliminary

iC-DC

2-CHANNEL BUCK/BOOST DC/DC CONVERTER

Rev A3, Page 16/19

DESCRIPTION OF THE APPLICATION

Selecting the coil

The coil should be designed for a maximum cut-off

current of 1 A. A small internal resistor in the coil re-

duces loss and increases converter efﬁciency. At a low

supply voltage this internal resistor can determine the

maximum available output current.

The EMI caused by the coil should be taken into con-

sideration. Toroidal core coils have little noise radia-

tion yet are expensive and difﬁcult to install. Bar core

coils are reasonably priced and easier to use yet have

a higher noise emittance. For modest EMI require-

ments inexpensive radio interference suppression coils

of several tens of µH are suitable∗.

Selecting the capacitors

Selecting back-up capacitors CVH, CVH1 and CVH2 is

unproblematic. As the residual ripple of intermediate

voltages VH1 and VH2 does not affect output volt-

ages VCC1 and VCC2 thanks to the back-end linear

regulators, a small capacitor is sufﬁcient without any

speciﬁc demands being made of the internal resis-

tor. A combination of electrolytic and ceramic capaci-

tors (e.g. 3.3 µF || 100 nF) is recommended. Before us-

ing tantalum capacitors, the user must verify whether

these are suitable for the residual AC amplitude (resid-

ual ripple) at pins VH1 and VH2.

Stability of the linear regulators across the entire load

area is guaranteed if the values given in the electrical

characteristics are selected for CVCC1 and CVCC2.

The suppression of interference voltage is improved

by using small capacitor series resistors. A combina-

tion of tantalum and ceramic capacitors is also recom-

mended in this case. If one of the two outputs remains

open, this capacitor can be omitted.

To avoid feedback of interference from supply voltage

VB onto output voltages VCC1 and VCC2, blocking

should be provided directly at pin VB. A combination

of tantalum and ceramic capacitors (e.g. 1 µF || 100 nF)

is also recommended in this case.

Printed circuit board layout

The GND path from the switching converter and from

each linear regulator should be strictly separated to

avoid cross couplings. The neutral point of all GND

paths is the GND connection at iC-DC. It is possible

and not critical, however, to route GND from supply VB

and the base point of capacitors CVH, CVH1 and CVH2

together to the neutral point. The capacitors should be

very close to their relevant pins, however.

Blocking capacitors for supply VB should be arranged

as close as possible to pins VB and GND. The capaci-

tors for outputs VCC1 and VCC2 should be placed di-

rectly at the load and not at the IC to also block inter-

ferences which are coupled via the wiring to the load.

The ground planes underneath the wiring of output

voltages VCC1, VCC2, POE1, and POE2 should be

kept separate from the ground planes of switching con-

verters VH, VH1, and VH2. The ground planes must

be connected up at a neutral point (see Figure 8).

The thermal pad should be connected to the PCB by

an appropriate ground plane. The resulting power dis-

sipation can be transferred to a different wiring layer,

e.g. a ground plane, by vias directly underneath the

IC.

Figure 8: Example layout: evaluation board DC1D

∗ e.g.: Siemens Matsushita B78108-S1224-J (22 µH/1 A, axial), TDK series NLC565050T-. . . (SMD), TOKO series 10RF459-. . . (SMD

shielded)

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