HT16L23 datasheet(13/43 Pages) HOLTEK

13 / 43 page

Rev. 1.00

November 16, 2011

HT16L23

Display Memory – RAM Structure

The display RAM is static 48×8-bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates

the “on” state of the corresponding LCD segment; similarly, logic 0 indicates the off state.

The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the

segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second,

third and fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively.

The LCD display duty can be 1/4 or 1/8 determined by a Duty bit contained in the Drive Mode Command. The

following diagram is a data transfer format for I2C or SPI interface.

MSB

LSB

LCD

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED

LCD Display or LED output data transfer format for I2C or SPI interface

1/4 Duty Display Mode

●

52×4 Display Mode

When the SP1 bit is set to “0” and the SP0 bit is set to “0” or “1”, the drive mode is selected as 52 segments by

4 commons. This drive mode is also the default setting after a reset.

Output

COM3

COM2

COM1

COM0

Output

COM3

COM2

COM1

COM0 Address

SEG1

SEG0

00H

SEG3

SEG2

01H

SEG5

SEG4

02H

↓

SEG51

SEG50

19H

Data

RAM mapping of 52×4 display mode

●

48×4 Display Mode

When the SP1 bit is set to “1” and the SP0 bit is set to “0”, the drive mode is selected as 48 segments by 4

commons together with 4 LED driving outputs.

Output

COM3

COM2

COM1

COM0

Output

COM3

COM2

COM1

COM0 Address

SEG1

SEG0

00H

SEG3

SEG2

01H

SEG5

SEG4

02H

↓

SEG47

SEG46

17H

Data

RAM mapping of 48×4 display mode

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