HIP2122, HIP2123

3

FN7670.0

December 23, 2011

Pin Descriptions

9 LD TDFN 10 LD TDFN SYMBOL

DESCRIPTION

1

1

VDD

Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS.

3

2

HB

High-side bootstrap supply voltage referenced to HS. Connect the positive side of bootstrap capacitor to this pin.

Bootstrap diode is on-chip.

4

3

HO

High-side output. Connect to gate of high-side power MOSFET.

5

4

HS

High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of

bootstrap capacitor to this pin.

8

8

LI

Low side driver input. For LI = 1, LO = 1 after programmed delay time; for LI = 0, LO = 0 with minimal delay.

7

7

HI

High side driver input. For HI = 1, HO = 1 after programmed delay time; for Hi = 0, HO = 0 with minimal delay.

9

9

VSS

Negative supply input, which will generally be ground.

10

10

LO

Low-side output. Connect to gate of low-side power MOSFET.

-

5

NC

No Connect. This pin is isolated from all other pins.

6

6

RDT

A resistor connected between this pin and VSS adds additional delay time to the normal rising edge propagation

delay.

-

-

EPAD

Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.

Ordering Information

PART NUMBER

(Notes 1, 2, 4)

PART

MARKING

INPUT

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

HIP2122FRTAZ

HIP 2122AZ

CMOS

- 40 to +125

10 Ld 4x4 TDFN

L10.4x4

HIP2123FRTAZ

HIP 2123AZ

3.3V/TTL

- 40 to +125

10 Ld 4x4 TDFN

L10.4x4

HIP2122FRTBZ (Note 3)

HIP 2122BZ

CMOS

- 40 to +125

9 Ld 4x4 TDFN

L9.4x4

HIP2123FRTBZ (Note 3)

HIP 2123BZ

3.3V/TTL

- 40 to +125

9 Ld 4x4 TDFN

L9.4x4

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

PbHfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted

for additional spacing.

4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2122, HIP2123. For more information on MSL please see tech brief

TB363.