HIP2122, HIP2123

11

FN7670.0

December 23, 2011

Functional Description

Functional Overview

The HIP2122/23 have independent control inputs, LI and HI, for

each output; LO and HO. When LI is low, LO is low and likewise,

when HI is low, HO is low. The output negative transitions occur

with minimal (and fixed) propagation delays.

The positive transitions of each output are delayed by the

programmed delay as set by RDT. With 80k, the delay is

nominally 25ns. With 8k, the delay is nominally 220ns. Resistors

values less than 8k and greater than 80k are not recommended.

Delaying the rising edge but not the falling edge of each output is

the technique that prevents shoot-thru. Please note that there is

no logic that prevents both outputs from being on if both inputs

are on simultaneously.

The enable pin, EN, when low, drives both outputs to a low state.

When the PWM input transitions, it is necessary to insure that

both bridge FETS are not on at the same time to prevent

shoot-through currents (break before make). The programmable

dead time forces both outputs to be off before either of the

results with a minimum nominal dead time of 50ns. Resistors

values less than 8k and greater than 80k are not recommended.

The high-side driver bias is established by the boot capacitor

connected between HB and HS. The charge on the boot capacitor

The current path to charge the boot capacitor occurs when the

low-side bridge FET is on. This charge current is limited in

amplitude by the inherent resistance of the boot diode and by the

drain-source voltage of the low-side FET. Assuming that the on

time of the low-side FET is sufficiently long to fully charge the

(less the boot diode drop and the low-side FET on voltage).

When the HI input transitions high, the high-side bridge FET is

driven on after the delay time. Because the HS node is connected

to the source of the high-side FET, the HS node will rise almost to

the level of the bridge voltage (less the conduction voltage across

the bridge FET). Because the boot capacitor voltage is referenced

volts above the HS node and the boot diode is reversed biased.

Because the high-side driver circuit is referenced to the HS node,

the HO output is now approximately VHB + VBRIDGE above

ground.

During the low to high transition of the HS node, the boot

capacitor sources the necessary gate charge to fully enhance the

high-side bridge FET gate. After the gate is fully charged, the boot

capacitor no longer sources the charge to the gate but continues

to provide bias current to the high-side driver. It is clear that the

charge of the boot capacitor must be substantially larger than

the required charge of the high-side FET and high-side driver

otherwise the boot voltage will sag excessively. If the boot

capacitor value is too small for the required maximum of on-time

of the high-side FET, the high-side UV lockout may engage

resulting with an unexpected operation.

Application Information

Selecting the Boot Capacitor Value

The boot capacitor value is chosen not only to supply the internal

bias current of the high-side driver but also, and more

significantly, to provide the gate charge of the driven FET without

causing the boot voltage to sag excessively. In practice, the boot

capacitor should have a total charge that is about 20 times the

gate charge of the driven power FET for approximately a 5% drop

in voltage after the charge has been transferred from the boot

capacitor to the gate capacitance.

The following parameters are required to calculate the value of

the boot capacitor for a specific amount of voltage droop. In this

example, the values used are arbitrary. They should be changed

to comply with the actual application.

The following equations calculate the total charge required for

the Period. This equation assumes that all of the parameters are

constant during the period duration. The error is insignificant if

the ripple is small.

Period = 1ms

This is the longest expected switching period

Worst case high side driver current when

xHO = high

error is not significant)

Gate-source resistor

(usually not needed)

Ripple = 5%

Desired ripple voltage on the boot capacitor

(larger ripple is not recommended)

From the FET vendor’s datasheet

Qgate80V = 64nC

From Figure 21

FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET

12

10

8

6

4

2

0

10

20

30

40

50

60

70

80

QG TOTAL GATE CHARGE (nC)

0