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LPC4310 Datasheet(PDF) 118 Page - NXP Semiconductors

Part # LPC4310
Description  32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals
PDF  149 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

LPC4310 Datasheet(HTML) 118 Page - NXP Semiconductors

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LPC4350_30_20_10
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Objective data sheet
Rev. 3.1 — 5 January 2012
118 of 149
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1]
Characterized but not implemented as production test.
[2]
Total average power consumption.
[3]
The driver is active only 20 % of the time.
11.11 Ethernet
Table 22.
Static characteristics: USB0 PHY pins[1]
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High-speed mode
Pcons
power consumption
[2] -68
-
mW
IDDA(3V3) analog supply current (3.3 V)
on pin USB0_VDDA3V3_DRIVER;
total supply current
[3]
-18
-
mA
during transmit
-
31
-
mA
during receive
-
14
-
mA
with driver tri-stated
-
14
-
mA
IDDD
digital supply current
-
7
-
mA
Full-speed/low-speed mode
Pcons
power consumption
[2] -15
-
mW
IDDA(3V3) analog supply current (3.3 V)
on pin USB0_VDDA3V3_DRIVER;
total supply current
-
3.5
-
mA
during transmit
-
5
-
mA
during receive
-
3
-
mA
with driver tri-stated
-
3
-
mA
IDDD
digital supply current
-
3
-
mA
Suspend mode
IDDA(3V3) analog supply current (3.3 V)
-
24
-
A
with driver tri-stated
-
24
-
A
with OTG functionality enabled
-
3
-
mA
IDDD
digital supply current
-
30
-
A
VBUS detector outputs
Vth
threshold voltage
for VBUS valid
4.4
-
-
V
for session end
0.2
-
0.8
V
for A valid
0.8
-
2
V
for B valid
2
-
4
V
Vhys
hysteresis voltage
for session end
-
150
10
mV
A valid
-
200
10
mV
B valid
-
200
10
mV
Table 23.
Dynamic characteristics: Ethernet
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Values guaranteed by
design.
Symbol Parameter
Conditions
Min
Max
Unit
RMII mode
fclk
clock frequency
for ENET_RX_CLK
[1]
-50
MHz
clk
clock duty cycle
[1]
50
50
%



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