9ZX21201 datasheet(7/16 Pages) IDT

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IDT®

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

1682B- 12/08/11

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

Electrical Characteristics - Skew and Differential Jitter Parameters

TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

CLK_IN, DIF[x:0]

tSPO_PLL

Input-to-Output Skew in PLL mode

nominal value @ 25°C, 3.3V

-100

100

1,2,4,5,8

CLK_IN, DIF[x:0]

tPD_BYP

Input-to-Output Skew in Bypass mode

nominal value @ 25°C, 3.3V

2.5

3.7

4.5

1,2,3,5,8

CLK_IN, DIF[x:0]

tDSPO_PLL

Input-to-Output Skew Varation in PLL mode

across voltage and temperature

-50

1,2,3,5,8

CLK_IN, DIF[x:0]

tDSPO_BYP

Input-to-Output Skew Varation in Bypass mode

across voltage and temperature

-250

250

1,2,3,5,8

CLK_IN, DIF[x:0]

tDTE

Random Differential Tracking error beween two

9ZX devices in Hi BW Mode

2.9

(rms)

1,2,3,5,8

CLK_IN, DIF[x:0]

tDSSTE

Random Differential Spread Spectrum Tracking

error beween two 9ZX devices in Hi BW Mode

1,2,3,5,8

DIF{x:0]

tSKEW_ALL

Output-to-Output Skew across all outputs

(Common to Bypass and PLL mode)

1,2,3,8

PLL Jitter Peaking

jpeak-hibw

LOBW#_BYPASS_HIBW = 1

1.8

2.5

7,8

PLL Jitter Peaking

jpeak-lobw

LOBW#_BYPASS_HIBW = 0

0.7

7,8

PLL Bandwidth

pllHIBW

LOBW#_BYPASS_HIBW = 1

3.1

MHz

8,9

PLL Bandwidth

pllLOBW

LOBW#_BYPASS_HIBW = 0

0.7

1.1

1.4

MHz

8,9

Duty Cycle

tDC

Measured differentially, PLL Mode

49.6

Duty Cycle Distortion

tDCD

Measured differentially, Bypass Mode

@100MHz

-2

-0.2

1,10

PLL mode

15.7

1,11

Additive Jitter in Bypass Mode

0.1

1,11

Notes for preceding table:

6.t is the period of the input clock

7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.

8. Guaranteed by design and characterization, not 100% tested in production.

9 Measured at 3 db down or half power point.

10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

11 Measured from differential waveform

3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.

4 This parameter is deterministic for a given device

5 Measured with scope averaging on to find mean value.

Jitter, Cycle to cycle

tjcyc-cyc

1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.

2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.

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