12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

1682B- 12/08/11

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

8

Power Management Table

Outputs

CKPWRGD•/PD#

DIF_IN/

DIF_IN#

SMBus

EN bit

OE# Pin

DIF(11:0)/

DIF(11:0)#

DFB_OUT/

DFB_OUT#

0X

X

X

Hi-Z

1

Hi-Z

1

OFF

0X

Hi-Z

1

Running

ON

1

0

Running

Running

ON

11

Hi-Z

1

Running

ON

NOTE:

1. Due to external pull down resistors, HI-Z results in Low/Low on the True/Complement outputs

Inputs

PLL State

1

Running

Control Bits/Pins

Electrical Characteristics - Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

PCIe Gen 1

32

86

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.8

3

ps

(rms)

1,2

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

1.9

3.1

ps

(rms)

1,2

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.45

1

ps

(rms)

1,2,4

QPI & SMI

(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)

0.20

0.5

ps

(rms)

1,5

QPI & SMI

(100MHz, 8.0Gb/s, 12UI)

0.14

0.3

ps

(rms)

1,5

QPI & SMI

(100MHz, 9.6Gb/s, 12UI)

0.12

0.2

ps

(rms)

1,5

PCIe Gen 1

0.10

10

ps (p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.13

0.3

ps

(rms)

1,2,6

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.10

0.7

ps

(rms)

1,2,6

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.10

0.3

ps

(rms)

1,2,4,6

QPI & SMI

(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)

0.09

0.3

ps

(rms)

1,5,6

QPI & SMI

(100MHz, 8.0Gb/s, 12UI)

0.09

0.1

ps

(rms)

1,5,6

QPI & SMI

(100MHz, 9.6Gb/s, 12UI)

0.09

0.1

ps

(rms)

1,5,6

Additive Phase Jitter,

Bypass mode

Phase Jitter, PLL Mode