ICS9DS400 datasheet(5/19 Pages) IDT

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IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread

1626

09/17/09

ICS9DS400

Four Output Differential Buffer for PCIe for Gen 2 with Spread

Advance Information

Absolute Max

Symbol

Parameter

Min

Max

Units

VDD

3.3V Supply Voltage

4.6

VIL

Input Low Voltage

GND-0.5

VIH

Input High Voltage

VDD+0.5V

Storage Temperature

-65

150

°C

Tcase

Case Temperature

115

°C

ESD prot

Input ESD protection

human body model

2000

Electrical Characteristics - Input/Supply/Common Output Parameters

TA =Over the Specified Operating Range; VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Input High Voltage

VIH

3.3 V +/-5%

VDD + 0.3

Input Low Voltage

VIL

3.3 V +/-5%

GND - 0.3

0.8

Input High Current

IIH

VIN = VDD

-5

IIL1

VIN = 0 V; Inputs with no pull-up resistors

-5

IIL2

VIN = 0 V; Inputs with pull-up resistors

-200

Operating Supply Current

IDD3.3OP

Full Active, CL = Full load;

125

all diff pairs driven

all differential pairs tri-stated

FiPLL

PCIe Mode (Bypass#/PLL= 1)

100.00

110

MHz

FiBYPASS

Bypass Mode ((Bypass#/PLL= 0)

400

MHz

Pin Inductance

Lpin

CIN

Logic Inputs, except SRC_IN

1.5

CINSRC_IN

SRC_IN differential clock inputs

1.5

2.7

1,4

COUT

Output pin capacitance

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st

clock

1,2

SS Modulation

Frequency

fMOD

Assuming 100 MHz input

(Triangular Modulation)

32.000

kHz

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

cycles

1,3

Tdrive_PD#

tDRVPD

DIF output enable after

PD# de-assertion

300

1,3

Tfall

Fall time of PD# and SRC_STOP#

Trise

Rise time of PD# and SRC_STOP#

SMBus Voltage

VMAX

Maximum input voltage

5.5

Low-level Output Voltage

VOL

@ IPULLUP

0.4

Current sinking at VOL

IPULLUP

SCLK/SDATA

Clock/Data Rise Time

tRSMB

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

SCLK/SDATA

Clock/Data Fall Time

tFSMB

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

SMBus Operating

Frequency

fMAXSMB

Maximum SMBus operating frequency

100

kHz

1,5

1Guaranteed by design and characterization, not 100% tested in production.

2See timing diagrams for timing requirements.

Input Low Current

Powerdown Current

Capacitance

5The differential input clock must be running for the SMBus to be active

Input Frequency

4SRC_IN input

IDD3.3PD

3Time from deassertion until outputs are >200 mV

ICS9DS400 Datasheet(PDF) 5 Page - Integrated Device Technology

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