9FG104DFILF datasheet(5/17 Pages) IDT

5 / 17 page

IDT®

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

1541C—12/16/10

ICS9FG104D

Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

Electrical Characteristics - DIF 0.7V Current Mode Differential Pair

TA = TAM BIENT; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2Ω, RP=49.9Ω, IREF = 475Ω

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Output Impedance

VO = Vx

3000

Ω

Voltage High

VHigh

660

850

Voltage Low

VLow

-150

150

Max Voltage

Vovs

1150

Min Voltage

Vuds

-300

Crossing Voltage (abs)

Vcross(abs)

250

550

Crossing Voltage (var)

d-Vcross

Crossing variation over all edges

140

Long Accuracy

ppm

see Tperiod min-max values

-300

300

ppm

1,2,5

400MHz nominal

2.49988

2.5000

2.5001

400MHz spread

2.4993

2.5133

2,3

333.33MHz nominal

2.99985

3.0000

3.0002

333.33MHz spread

2.9991

3.016

2,3

266.66MHz nominal

3.74981

3.7500

3.7502

266.66MHz spread

3.7489

3.77

2,3

200MHz nominal

4.9998

5.0000

5.0003

200MHz spread

4.9985

5.0266

2,3

166.66MHz nominal

5.9997

6.0000

6.0003

166.66MHz spread

5.9982

6.0320

2,3

133.33MHz nominal

7.4996

7.5000

7.5004

133.33MHz spread

7.4978

5.4000

2,3

100.00MHz nominal

9.9995

10.0000 10.0005

100.00MHz spread

9.9970

10.0533

2,3

400MHz nominal/spread

2.4143

1,2

333.33MHz nominal/spread

2.9141

1,2

266.66MHz nominal/spread

3.6639

1,2

200MHz nominal/spread

4.8735

1,2

166.66MHz nominal/spread

5.8732

1,2

133.33MHz nominal/spread

7.3728

1,2

100.00MHz nominal/spread

9.8720

1,2

Rise Time

VOL = 0.175V, VOH = 0.525V

175

700

Fall Time

VOH = 0.525V VOL = 0.175V

175

700

Rise Time Variation

d-tr

125

Fall Time Variation

d-tf

125

Duty Cycle

dt3

Measured Differentially

Skew, output to output

tsk3

VT = 50%

Jitter, Cycle to cycle

tjcyc-cyc

Measured Differentially

1Guaranteed by design and characterization, not 100% tested in production.

3 Figures are for down spread.

Absolute min period

Statistical measurement on

single ended signal using

oscilloscope math function.

5 +/- 50 ppm at any frequency with spread off

4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit

http://www.pcisig.com for additional details

2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is tuned to 0

Measurement on single ended

signal using absolute value.

Tabsmin

Average period

Tperiod

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