AD9608

Rev. 0 | Page 7 of 40

Parameter

Temp

Min

Typ

Max

Unit

LVDS Mode—DRVDD = 1.8 V

Full

290

345

400

mV

Full

1.15

1.25

1.35

V

Full

160

200

230

mV

Full

1.15

1.25

1.35

V

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless

otherwise noted.

Table 4.

AD9608-105

AD9608-125

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

1000

1000

MHz

Conversion Rate1

DCS Enabled

Full

20

105

20

125

MSPS

DCS Disabled

Full

10

105

10

125

MSPS

Full

9.52

8

ns

Full

4.76

4

ns

Full

1.0

1.0

ns

Full

0.07

0.07

ps rms

DATA OUTPUT PARAMETERS

CMOS Mode

CMOS Mode (DRVDD = 1.8 V)

Full

1.8

2.9

4.4

1.8

2.9

4.4

ns

Full

2.0

3.1

4.4

2.0

3.1

4.4

ns

Full

−1.2

−0.1

+1.0

−1.2

−0.1

+1.0

ns

LVDS Mode (DRVDD = 1.8 V)

Full

2.4

2.4

ns

Full

4.4

4.4

ns

Full

−0.1

+0.2

+0.5

−0.1

+0.2

+0.5

ns

CMOS Mode Pipeline Delay (Latency)

Full

16

16

Cycles

LVDS Mode Pipeline Delay (Latency)

Channel A/Channel B

Full

16/16.5

16/16.5

Cycles

Wake-Up Time (Power-Down)3

Full

350

350

μs

Wake-Up Time (Standby)

Full

250

250

ns

Out-of-Range Recovery Time

Full

2

2

Cycles

).

ble 18