AM3359 datasheet(82/197 Pages) TI1

82 / 197 page

AM3359, AM3358, AM3357

AM3356, AM3354, AM3352

SPRS717B

– OCTOBER 2011 – REVISED JANUARY 2012

www.ti.com

Table 3-4. Recommended Operating Conditions (continued)

PARAMETER

MIN

NOM

MAX

UNIT

SUPPLY NAME

DESCRIPTION

Voltage range for the USB ID

USB1_ID(4)

1.71

1.8

1.89

input

Commercial Temperature

Operating Temperature

Industrial Temperature

-40

°C

Range, Tj

Extended Temperature

-40

105

(1) Not available on the ZCE package. VDD_MPU is merged with VDD_CORE on the ZCE package.

(2) This supply is sourced from an internal LDO when RTC_KALDO_ENn is low. If RTC_KALDO_ENn is high, this supply must be sourced

from an external power supply.

(3) VDDS should be supplied irrespective of 1.8-V or 3.3-V mode of operation of the dual-voltage IOs.

(4) Not available on the ZCE package.

Table 3-5. Operating Performance Points for ZCZ Package(1)

OPP

VDD_MPU(2)

VDD_CORE(2)

ARM (A8)

DDR3(3)

DDR2(3)

mDDR(3)

L3/L4

Turbo

1.26 V

±4%

1.1 V

±4%

720 MHz

303 MHz(4)

266 MHz

200 MHz

200/100 MHz

OPP120

1.2 V

±4%

1.1 V

±4%

600 MHz

303 MHz(4)

266 MHz

200 MHz

200/100 MHz

OPP100

1.1 V

±4%

1.1 V

±4%

500 MHz

303 MHz(4)

266 MHz

200 MHz

200/100 MHz

OPP50

0.95 V

±4%

0.95 V

±4%

275 MHz

125 MHz

90 MHz

100/50 MHz

(1) Frequencies in this table indicate maximum performance for a given OPP condition.

(2) Interfaces in this row are validated and available on OPP50.

(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate

(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

(4) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard speed bin DDR3 memory devices.

Therefore, all standard speed bin DDR3 memory devices are required to operate at 303 MHz.

Table 3-6. Operating Performance Points for ZCE Package(1)

OPP

VDD_CORE(2)

ARM (A8)

DDR3(3)

DDR2(3)

mDDR(3)

L3/L4

OPP100

1.1 V

±4%

500 MHz

303 MHz(4)

266 MHz

200 MHz

200/100 MHz

OPP50

0.95 V

±4%

275 MHz

125 MHz

90 MHz

100/50 MHz

(1) Frequencies in this table indicate maximum performance for a given OPP condition.

(2) Interfaces in this row are validated and available on OPP50.

(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate

(DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

(4) The JEDEC JESD79-3E specification defines the maximum clock period of 3.3 ns for all standard-speed bin DDR3 memory devices.

Therefore, all standard-speed bin DDR3 memory devices are required to operate at 303 MHz.

Device Operating Conditions

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