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HT45F43 Datasheet(PDF) 50 Page - Holtek Semiconductor Inc |
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HT45F43 Datasheet(HTML) 50 Page - Holtek Semiconductor Inc |
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50 / 152 page  Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with several configuration options control the overall operation of the Watchdog Timer. WDTC Register Bit 76543210 Name FSYSON WS2 WS1 WS0 WDTEN3 WDTEN2 WDTEN1 WDTEN0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 01111010 Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit6~4 WS2, WS1, WS0 : WDT time-out period selection 000: 2 13/f S 001: 2 14/f S 010: 2 15/f S 011: 2 16/f S 100: 2 17/f S 101: 2 18/f S 110: 2 19/f S 111: 2 20/f S These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. Bit3~0 WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control 1010: Disable Other: Enable Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Some of the Watchdog Timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. In addition to a configuration option to enable/disable the Watchdog Timer, there are also four bits, WDTEN3~WDTEN0, in the WDTC register to offer an additional enable/disable control of the Watchdog Timer. To disable the Watchdog Timer, as well as the configuration option being set to disable, the WDTEN3~WDTEN0 bits must also be set to a specific value of ²1010². Any other values for these bits will keep the Watchdog Timer enabled, irrespective of the configuration enable/disable setting. After power on these bits will have the value of 1010. If the Watchdog Timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. Note that if the Watchdog Timer has been disabled, then any instruction relating to its operation will result in no operation. WDT Configuration Option WDTEN3~WDTEN0 Bits WDT WDT Enable xxxx Enable WDT Disable Except 1010 Enable WDT Disable 1010 Disable Watchdog Timer Enable/Disable Control Rev. 1.20 50 September 15, 2011 HT45F23/HT45F43 8-Bit Flash MCU with Op Amps & Comparators |
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