HT67F60 datasheet(117/242 Pages) HOLTEK

117 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

116

March 06 , 2012

Rev. 1.50

117

March 06 , 2012

CTM, PWM Mode, Edge-aligned Mode, T0DPX=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

Duty

CCRA

If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA = 128,

The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.

If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

CTM, PWM Mode, Edge-aligned Mode, T0DPX=1

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

CCRA

Duty

128

256

384

512

640

768

896

1024

The PWM output period is determined by the CCRA register value together with the TM clock

while the PWM duty cycle is defined by the CCRP register value.

Counter Value

CCRP

CCRA

TnON

TnPAU

TnPOL

CCRP Int.

Flag TnPF

CCRA Int.

Flag TnAF

TM O/P Pin

(TnOC=1)

Time

Counter cleared

by CCRP

Pause Resume

Counter Stop if

TnON bit low

Counter Reset when

TnON returns high

TnDPX = 0; TnM [1:0] = 10

PWM Duty Cycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

when TnPOL = 1

PWM Period

set by CCRP

TM O/P Pin

(TnOC=0)

PWM Mode — TnDPX = 0

Note: 1. Here TnDPX=0 – Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when TnIO [1:0] = 00 or 01

4. The TnCCLR bit has no influence on PWM operation

HT67F60 Datasheet(PDF) 117 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 117 Page - Holtek Semiconductor Inc

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