HT67F60 datasheet(154/242 Pages) HOLTEK

154 / 242 page

Rev. 1.50

154

March 06 , 2012

Rev. 1.50

155

March 06 , 2012

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPRO

A/D Operation

The START bit in the ADCR0 register is used to start and reset the A/D converter. When the

microcontroller sets this bit from low to high and then low again, an analog to digital conversion

cycle will be initiated. When the START bit is brought from low to high but not low again, the

EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It

is the START bit that is used to control the overall start operation of the internal analog to digital

converter.

The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion

process is complete. This bit will be automatically set to "0" by the microcontroller after a

conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in

the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal

will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/

D internal interrupt address for processing. If the A/D internal interrupt is disabled, the

microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has

been cleared as an alternative method of detecting the end of an A/D conversion cycle.

The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen

to be either fSYS or a subdivided version of fSYS

The division ratio value is determined by the

ADCK2~ADCK0 bits in the ADCR1 register.

Although the A/D clock source is determined by the system clock fSYS, and by bits

ADCK2~ADCK0, there are some limitations on the maximum A/D clock source speed that can be

selected. As the minimum value of permissible A/D clock period, tADCK, is 0.5ms, care must be taken

for system clock frequencies equal to or greater than 4MHz. For example, if the system clock

operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to "000". Doing so

will give A/D clock periods that are less than the minimum A/D clock period which may result in

inaccurate A/D conversion values. Refer to the following table for examples, where values marked

with an asterisk * show where, depending upon the device, special care must be taken, as the values

may be less than the specified minimum A/D Clock Period.

fSYS

A/D Clock Period (tADCK)

ADCK2,

ADCK1,

ADCK0

=000

(fSYS)

ADCK2,

ADCK1,

ADCK0

=001

(fSYS/2)

ADCK2,

ADCK1,

ADCK0

=010

(fSYS/4)

ADCK2,

ADCK1,

ADCK0

=011

(fSYS/8)

ADCK2,

ADCK1,

ADCK0

=100

(fSYS/16)

ADCK2,

ADCK1,

ADCK0

=101

(fSYS/32)

ADCK2,

ADCK1,

ADCK0

=110

(fSYS/64)

ADCK2,

ADCK1,

ADCK0

=111

1MHz

1µs

2µs

4µs

8µs

16µs

32µs

64µs

Undefined

2MHz

500ns

1µs

2µs

4µs

8µs

16µs

32µs

Undefined

4MHz

250ns*

500ns

1µs

2µs

4µs

8µs

16µs

Undefined

8MHz

125ns*

250ns*

500ns

1µs

2µs

4µs

8µs

Undefined

12MHz

83ns*

167ns*

333ns*

667ns

1.33µs

2.67µs

5.33µs

Undefined

A/D Clock Period Examples

Controlling the power on/off function of the A/D converter circuitry is implemented using the

ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the

ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as

indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no

pins are selected for use as A/D inputs by clearing the ACE11~ACE0 bits in the ACERH and

ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power

conscious applications it is therefore recommended that the ADOFF is set high to reduce power

consumption when the A/D converter function is not being used.

HT67F60 Datasheet(PDF) 154 Page - Holtek Semiconductor Inc

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