HT67F60 datasheet(167/242 Pages) HOLTEK

167 / 242 page

HT67F30/HT67F40/HT67F50/HT67F60

TinyPowerTM A/D Flash Type 8-Bit MCU with LCD & EEPROM

Rev. 1.50

166

March 06 , 2012

Rev. 1.50

167

March 06 , 2012

SPI Communication

After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when

data is written to the SIMD register, transmission/reception will begin simultaneously. When the

data transfer is complete, the TRF flag will be set automatically, but must be cleared using the

application program. In the Slave Mode, when the clock signal from the master has been received,

any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the

SIMD register. The master should output an SCS signal to enable the slave device before a clock

signal is provided. The slave data to be transferred should be well prepared at the appropriate

moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and

CKEG bit. The accompanying timing diagram shows the relationship between the slave data and

SCS signal for various configurations of the CKPOLB and CKEG bits.

The SPI will continue to function even in the IDLE Mode.

SC K (C KP OL B= 1, C KE G= 0)

SI ME N, C SE N= 1

SI ME N= 1, C SE N= 0 (E xt er nal P ul l- Hi gh )

SC K (C KP OL B= 0 , C KE G= 0)

SC K (C KP OL B= 1 , C KE G= 1)

SC K (C KP OL B= 0 , C KE G= 1)

SD O (C KE G= 0)

SD O (C KE G= 1)

SC S

SD I Da ta C apt ur e

D7 /D 0D 6/ D1

D5 /D 2D 4/ D3 D3 /D 4D 2/ D5

D1 /D 6D 0/ D7

D7 /D 0D 6/ D1

D5 /D 2D 4/ D3 D3 /D 4D 2/ D5

D1 /D 6D 0/ D7

Wr it e to S IM D

SPI Master Mode Timing

SC K (C KP OL B= 1)

SC K (C KP OL B= 0)

SD O

SC S

SD I Da ta C apt ur e

D7 /D 0D 6/ D1

D5 /D 2D 4/ D3 D3 /D 4D 2/ D5

D1 /D 6D 0/ D7

Wr it e to S IM D

(S DO d oe s not c hange un ti l fi rs t SC K edge )

SPI Slave Mode Timing – CKEG=0

HT67F60 Datasheet(PDF) 167 Page - Holtek Semiconductor Inc

HT67F60 Datasheet(HTML) 167 Page - Holtek Semiconductor Inc

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