HT95R22 datasheet(19/52 Pages) HOLTEK

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HT95R22

Rev. 1.00

January 6, 2009

on/off bit, which is bit 4 of the Timer Control Register,

and known as T0ON and T1ON, provides the basic

on/off control of the Timer/Event Counter. Setting the bit

high allows the Timer/Event Counter to run, clearing the

bit stops it running. If Timer/Event Counter 0 is in the

event count or pulse width measurement mode, the ac-

tive transition edge level type is selected by the logic

level of bit 3 of the Timer Control Register which is

known as T0E.

Configuring the Timer Mode

This mode is available for both Timer/Event Counters. In

this mode, the Timer/Event Counters can be utilised to

measure fixed time intervals, providing an internal inter-

rupt signal each time the Timer/Event Counter over-

flows. To operate in this mode, the Operating Mode

Select bit pair in the Timer Control Register must be set

to the correct value as shown.

Control Register Operating Mode

Select Bits for the Timer Mode

Bit7 Bit6

In this mode the internal clock, is used as the

Timer/Event Counter clock. After the other bits in the

Timer Control Register have been setup, the enable bit,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter to run. Each

time an internal clock cycle occurs, the Timer/Event

Counter increments by one. When it is full and over-

flows, an interrupt signal is generated and the

Timer/Event Counter will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the Interrupt

Control Register, is reset to zero.

Configuring the Event Counter Mode

This mode is only available for Timer/Event Counter 0.

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by Timer/Event Counter 0. To operate in this

mode, the Operating Mode Select bit pair in the Timer

Control Register must be set to the correct value as

shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7 Bit6

In this mode the external timer pin is used as the

Timer/Event Counter 0 clock source, however it is not di-

vided by the internal prescaler. After the other bits in the

Timer Control Register have been setup, the enable bit,

which is bit 4 of the Timer Control Register, can be set

high to enable the Timer/Event Counter to run. If the Ac-

tive Edge Select bit, which is bit 3 of the Timer Control

each time the external timer pin receives a low to high

transition. If the Active Edge Select bit is high, the coun-

ter will increment each time the external timer pin re-

ceives a high to low transition. When it is full and

overflows, an interrupt signal is generated and

Timer/Event Counter 0 will reload the value already

loaded into the preload register and continue counting.

The interrupt can be disabled by ensuring that the

Timer/Event Counter 0 Interrupt Enable bit in the Inter-

rupt Control Register, is reset to zero.

To ensure that the timer pin is configured to operate as

an event counter input pin the Timer Control Register

must place Timer/Event Counter 0 in the Event

Counting Mode. It should be noted that in the event

counting mode, even if the microcontroller is in the

Power Down Mode, Timer/Event Counter 0 will continue

to record externally changing logic events on the timer

input pin. As a result when the timer overflows it will gen-

erate a timer interrupt and corresponding wake-up

source.

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Diagram

T i m e r + 2

E x t e r n a l T i m e

P i n I n p u t

T E = 1

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Diagram

HT95R22 Datasheet(PDF) 19 Page - Holtek Semiconductor Inc

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