ANALOG PRODUCTS DIVISION

561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715

www.protekanalog.com

PA5155

Low Power Stereo Audio CODEC

With Headphone Amplifier

95244 Rev.0. 01/10

NOT FOR USE IN LIFE SUPPORT SYSTEMS

Figure 2 Complete Data Transfer for 2-wire Interface

A master controller initiates the transmission by sending

a “start” signal, which is defined as a high-to-low transition at SDA while SCL

is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be

001000x,where x equals AD0 (pin CE). The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received,

the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the

communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high.

In 2-

wire interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 3

and Table 4. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W

to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the

I

Table 3 Write Data to Register in 2-wire Interface Mode

Chip Address

R/W

Register Address

Data to be written

001000

AD0

0

ACK

RAM

ACK

DATA

Table 4 Read Data from Register in 2-wire Interface Mode

Chip Address

R/W

Register Address

001000

AD0

0

ACK

RAM

Chip Address

R/W

Data to be read

001000

AD0

1

ACK

DATA

CONFIGURATION REGISTER DEFINITION

SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total

of 53 user programmable 8-bit registers in this device. These registers control the operations of DAC. External master controller can

access these registers by using the slave address specified in RAM (Register Address Map) register as shown in the Table 5.