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VREF _ TRIM

0.6

STEP _ VREF _ MARGIN _ HIGH

VREF _ TRIM

0.6

STEP _ VREF _ MARGIN _ LOW

VREF _ TRIM

0.6

(

)

OUT

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TPS40422

www.ti.com

SLUSAQ4A

– OCTOBER 2011 – REVISED DECEMBER 2011

These output states are set using the OPERATION command. The FB pin reference voltage is calculated as

follows in each of these states.

No margin voltage:

(7)

Margin high voltage state:

(8)

Margin low state:

where

•

VFB is the FB pin voltage

•

VREF_TRIM is the offset voltage in volts to be applied to the output voltage

•

VREF_MARGIN_HIGH is the requested margin high voltage

•

VREF_MARGIN_LOW is the requested margin low voltage

(9)

For these conditions, the output voltage is shown in Equation 10.

where

•

VFB is the pin voltage calculated in Equation 7, Equation 8 or Equation 9 depending on the output state

•

R2 and R1 are in consistent units from Figure 9

•

VOUT is the output voltage

(10)

NOTE

The sum of the margin and trim voltages cannot be more tha between

–20% and +10% of

the nominal output voltage. The FB pin voltage can deviate no more that this from the

nominal 600 mV.

Reading the Output Current

The average output current for the converter is readable using the READ_IOUT command. The results of this

command support only positive or current sourced from the converter. If the converter is sinking current the result

of this command is a reading of 0 A.

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