TPS40422 datasheet(13/54 Pages) TI1

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TPS40422

www.ti.com

SLUSAQ4A

– OCTOBER 2011 – REVISED DECEMBER 2011

APPLICATION INFORMATION

General Description/Control Architecture

The TPS40422 is a flexible synchronous buck controller. It can be used as a dual-output controller, or as a

two-phase single-output controller. It operates with a wide input range from 4.5 V to 20 V and generates accurate

regulated output as low as 600 mV.

In dual output mode, voltage mode control with input feed-forward architecture is implemented. With this

architecture, the benefits are less noise sensitivity, no control instability issues for small DCR applications, and a

smaller minimum controllable on-time, often desired for high conversion ratio applications.

In two-phase single-output mode, a current-sharing loop is implemented to ensure a balance of current between

phases. Because the induced error current signal to the loop is much smaller when compared to the PWM ramp

amplitude, the control loop is modeled as voltage mode with input feed-forward.

DESIGN NOTE

To operate the device in two-phase mode, tie the FB2 pin to the BP6 pin and tie the

COMP1 pin to the COMP2 pin. These connections must be made before applying voltage

to the VDD pin.

PMBus General Description

Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol

Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS40422 supports both the 100 kHz and

400 kHz bus timing requirements. The TPS40422 does not stretch pulses on the PMBus when communicating

with the master device.

Communication over the TPS40422 device PMBus interface can either support the Packet Error Checking (PEC)

scheme or not. If the master supplies CLK pulses for the PEC byte, it is used. If the CLK pulses are not present

before a STOP, the PEC is not used.

The TPS40422 supports a subset of the commands in the PMBus 1.1 specification. Most all of the controller

parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require

data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the

command and altering the exponent is not supported. Direct format data input or output is not supported by the

TPS40422. See the SUPPORTED COMMANDS section for specific details.

The TPS40422 also supports the SMBALERT response protocol. The SMBALERT response protocol is a

mechanism by which a slave (the TPS40422) can alert the bus master that it wants to talk. The master

processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the

alert response address. Only the slave that caused the alert acknowledges this request. The host performs a

modified receive byte operation to get the slave

’s address. At this point, the master can use the PMBus status

commands to query the slave that caused the alert. For more information on the SMBus alert response protocol,

see the System Management Bus (SMBus) specification.

The TPS40422 contains non-volatile memory that is used to store configuration settings and scale factors. The

settings programmed into the device are not automatically saved into this non-volatile memory though. The

STORE_USER_ALL command must be used to commit the current settings to non-volatile memory as device

defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed

descriptions.

Voltage Reference

The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference

voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final

regulation voltage. The 0.5-% tolerance on the reference voltage allows the user to design a very accurate power

supply.

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