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Data Sheet

AD5735

Rev. B | Page 41 of 48

DIGITAL SLEW RATE CONTROL

The digital slew rate control feature of the AD5735 allows the

user to control the rate at which the output value changes. This

feature is available on both the current and voltage outputs. With

the slew rate control feature disabled, the output value changes

at a rate limited by the output drive circuitry and the attached

load. To reduce the slew rate, the user can enable the digital slew

rate control feature using the SREN bit of the slew rate control

When slew rate control is enabled, the output, instead of slewing

directly between two values, steps digitally at a rate defined by

the SR_CLOCK and SR_STEP parameters. These parameters

are accessible via the slew rate control register (see Table 29).

•

SR_CLOCK defines the rate at which the digital slew is

updated; for example, if the selected update rate is 8 kHz,

the output is updated every 125 µs.

•

SR_STEP defines by how much the output value changes

at each update.

Together, these parameters define the rate of change of the

output value. Table 34 and Table 35 list the range of values for

the SR_CLOCK and SR_STEP parameters, respectively.

Table 34. Slew Rate Update Clock Options

SR_CLOCK

Update Clock Frequency1

0000

64 kHz

0001

32 kHz

0010

16 kHz

0011

8 kHz

0100

4 kHz

0101

2 kHz

0110

1 kHz

0111

500 Hz

1000

250 Hz

1001

125 Hz

1010

64 Hz

1011

32 Hz

1100

16 Hz

1101

8 Hz

1110

4 Hz

1111

0.5 Hz

These clock frequencies are divided down from the 13 MHz internal

oscillator (see Table 1, Figure 67, and Figure 68).

Table 35. Slew Rate Step Size Options

SR_STEP

Step Size (LSB)

000

001

010

011

100

101

110

128

111

256

The following equation describes the slew rate as a function of

the step size, the update clock frequency, and the LSB size.

Size

LSB

Frequency

Clock

Update

Size

Step

Change

Output

Rate

Slew

where:

Slew Rate is expressed in seconds.

Output Change is expressed in amperes for IOUT_x or in

volts for VOUT_x.

The update clock frequency for any given value is the same for

all output ranges. The step size, however, varies across output

ranges for a given value of step size because the LSB size is

different for each output range.

When the slew rate control feature is enabled, all output changes

occur at the programmed slew rate (see the DC-to-DC Converter

Settling Time section for more information). For example, if the

CLEAR pin is asserted, the output slews to the clear value at the

programmed slew rate (assuming that the channel is enabled to

be cleared).

If more than one channel is enabled for digital slew rate control,

care must be taken when asserting the CLEAR pin. If a channel

under slew rate control is slewing when the CLEAR pin is asserted,

other channels under slew rate control may change directly to

their clear code not under slew rate control.

DYNAMIC POWER CONTROL

When configured in current output mode, the AD5735 provides

integrated dynamic power control using a dc-to-dc boost converter

circuit. This circuit reduces power consumption compared with

standard designs.

In standard current input module designs, the load resistor

values can range from typically 50 Ω to 750 Ω. Output module

systems must source enough voltage to meet the compliance

voltage requirement across the full range of load resistor values.

For example, in a 4 mA to 20 mA loop when driving 20 mA, a

compliance voltage of >15 V is required. When driving 20 mA

into a 50 Ω load, a compliance voltage of only 1 V is required.

The AD5735 circuitry senses the output voltage and regulates

this voltage to meet the compliance requirements plus a small

headroom voltage. The AD5735 is capable of driving up to

24 mA through a 1 kΩ load.

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