AD5686R datasheet(19/32 Pages) AD

19 / 32 page

Data Sheet

AD5696R/AD5695R/AD5694R

Rev. 0 | Page 19 of 32

SERIAL INTERFACE

The AD5696R/AD5695R/AD5694R have 2-wire I2C-

compatible serial interfaces (refer to I2

C-Bus Specification, Version

2.1, January 2000, available from Philips Semiconductor). See

Figure 2 for a timing diagram of a typical write sequence. The

AD5696R/AD5695R/AD5694R can be connected to an I2C bus as

a slave device, under the control of a master device. The

AD5696R/AD5695R/AD5694R support standard (100 kHz)

and fast (400 kHz) data transfer modes. Support is not provided

for 10-bit addressing and general call addressing.

Input Shift Register

The input shift register of the AD5696R/AD5695R/AD5694R is

24 bits wide. Data is loaded into the device as a 24-bit word

under the control of a serial clock input, SCL. The first eight

MSBs make up the command byte. The first four bits are the

command bits (C3, C2, C1, C0) that control the mode of

operation of the device (see Table 7). The last 4 bits of first byte

are the address bits (DAC A, DAC B, DAC C, DAC D) (see

Table 8).

The data-word comprises 16-bit, 14-bit, or 12-bit input code,

followed by four, two, or zero don’t care bits for the AD5696R,

AD5695R, and AD5694R, respectively (see Figure 48, Figure 49,

and Figure 50). These data bits are transferred to the input

Commands can be executed on individual DAC channels,

combined DAC channels, or on all DACs, depending on the

address bits selected.

Table 7. Command Definitions

Command

Description

No operation

Write to Input Register n (dependent on LDAC)

Update DAC Register n with contents of Input

Write to and update DAC Channel n

Power down/power up DAC

Hardware LDAC mask register

Software reset (power-on reset)

Internal reference setup register

Reserved

…

Reserved

Table 8. Address Commands

Address (n)

Selected DAC Channel1

DAC D

DAC C

DAC B

DAC A

DAC B

DAC C

DAC D

DAC A and DAC B1

All DACs

Any combination of DAC channels can be selected using the address bits.

Figure 48. AD5696R Input Shift Register Content

Figure 49. AD5695R Input Shift Register Content

Figure 50. AD5694R Input Shift Register Content

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

D13

D12

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DAC D DAC C DAC B DAC A

D15

D14

D13

D12

D11

D10

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

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