AD5686R datasheet(24/32 Pages) AD

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AD5696R/AD5695R/AD5694R

Data Sheet

Rev. 0 | Page 24 of 32

LOAD DAC (HARDWARE LDAC PIN)

The AD5696R/AD5695R/AD5694R DACs have double

buffered interfaces consisting of two banks of registers:

input registers and DAC registers. The user can write to

any combination of the input registers. Updates to the DAC

Figure 54. Simplified Diagram of Input Loading Circuitry for a Single DAC

Instantaneous DAC Updating (LDAC Held Low)

LDAC is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

the DAC register are updated on the 24th clock and the output

begins to change (see Table 13).

Deferred DAC Updating (LDAC is Pulsed Low)

LDAC is held high while data is clocked into the input register

using Command 0001. All DAC outputs are asynchronously

updated by taking LDAC low after the 24th clock. The update

now occurs on the falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for this software LDAC function.

Address bits are ignored. Writing to the DAC, using Command

0101, loads the 4-bit LDAC register (DB3 to DB0). The default

for each channel is 0; that is, the LDAC pin works normally.

Setting the bits to 1 forces this DAC channel to ignore transitions

on the LDAC pin, regardless of the state of the hardware LDAC

pin. This flexibility is useful in applications where the user

wishes to select which channels respond to the LDAC pin.

Table 12. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits

(DB3 to DB0)

LDAC Pin

LDAC Operation

1 or 0

Determined by the LDAC pin.

DAC channels update and

override the LDAC pin. DAC

channels see LDAC as 1.

1 X = don’t care.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 12). Setting the LDAC

bits (DB0 to DB3) to 0 for a DAC channel means that this

channel’s update is controlled by the hardware LDAC pin.

Table 13. Write Commands and LDAC Pin Truth Table1

Commands

Description

Hardware LDAC

Pin State

Input Register

Contents

DAC Register Contents

0001

Write to Input Register n (dependent on LDAC)

VLOGIC

Data update

No change (no update)

GND2

Data update

0010

Update DAC Register n with contents of Input

VLOGIC

No change

Updated with input register

contents

GND

No change

Updated with input register

contents

0011

Write to and update DAC Channel n

VLOGIC

Data update

GND

Data update

1 A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that

are not masked (blocked) by the LDAC mask register.

2 When LDAC is permanently tied low, the LDAC mask bits are ignored.

SDO

SCL

VOUT

DAC

INPUT SHIFT

OUTPUT

AMPLIFIER

LDAC

REFIN

INPUT

12-/14-/16-BIT

DAC

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