AD6672 datasheet(8/32 Pages) AD

8 / 32 page

AD6672

Rev. 0 | Page 8 of 32

SWITCHING SPECIFICATIONS

Table 4.

Parameter

Temperature

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

625

MHz

Conversion Rate1

Full

250

MSPS

CLK Period—Divide-by-1 Mode (tCLK)

Full

CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled

Full

1.8

2.0

2.2

Divide-by-1 Mode, DCS Disabled

Full

1.9

2.0

2.1

Divide-by-2 Mode Through Divide-by-8 Mode

Full

0.8

Aperture Delay (tA)

Full

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

Full

4.1

4.7

5.2

DCO Propagation Delay (tDCO)

Full

4.7

5.3

5.8

DCO-to-Data Skew (tSKEW)

Full

0.3

0.5

0.7

Pipeline Delay (Latency)—NSR Disabled

Full

Cycles

Pipeline Delay (Latency)—NSR Enabled

Full

Cycles

Wake-Up Time (from Standby)

Full

μs

Wake-Up Time (from Power-Down)

Full

100

μs

Out-of-Range Recovery Time

Full

Cycles

1 Conversion rate is the clock rate after the divider.

Timing Diagram

N + 5

N + 4

N + 3

N + 2

N + 1

N – 1

tCH

tCLK

tDCO

tPD

tSKEW

CLK+

CLK–

DCO–

DCO+

0/D0±

(LSB)

D9±/D10±

(MSB)

VIN

ODD/EVEN

N – 10

D10

N – 10

N – 9

D10

N – 9

N – 8

D10

N – 8

N – 7

D10

N – 7

N – 6

N – 9

N – 8

N – 7

N – 6

N – 7

Figure 2. LVDS Data Output Timing

AD6672 Datasheet(PDF) 8 Page - Analog Devices

AD6672 Datasheet(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL