AD6672 datasheet(3/32 Pages) AD

3 / 32 page

AD6672

Rev. 0 | Page 3 of 32

When the NSR block is disabled, the ADC data is provided directly

to the output at a resolution of 11 bits. This allows the AD6672

to be used in telecommunication applications, such as a digital

predistortion observation path, where wider bandwidths are

required.

After digital signal processing, multiplexed output data is

routed into one 11-bit output port such that the maximum

data rate is 500 Mbps (DDR). This output is LVDS and

supports ANSI-644 levels.

The AD6672 receiver digitizes a wide spectrum of IF frequencies.

This IF sampling architecture greatly reduces component cost

and complexity compared with traditional analog techniques or

less integrated digital methods.

Flexible power-down options allow significant power savings.

Programming for device setup and control is accomplished

using a 3-wire, SPI-compatible serial interface with numerous

modes to support board level system testing.

The AD6672 is available in a 32-lead, RoHS-compliant LFCSP

and is specified over the industrial temperature range of −40°C

to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

Integrated 11-bit, 250 MSPS ADC with a noise shaping

requantizer option.

Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating LVDS outputs.

On-chip 1-to-8 integer clock divider function to support a

wide range of clocking.

Noise shaping requantizer function allows attaining improved

SNR within a reduced frequency band. With NSR enabled,

the AD6672 supports up to 82 MHz at 250 MSPS.

Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, test modes, and voltage

reference mode.

AD6672 Datasheet(PDF) 3 Page - Analog Devices