AD9634 datasheet(7/32 Pages) AD

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AD9634

Rev. 0 | Page 7 of 32

SWITCHING SPECIFICATIONS

Table 4.

AD9634-170

AD9634-210

AD9634-250

Parameter

Temperature

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS1

Input Clock Rate

Full

625

MHz

Conversion Rate2

DCS Enabled

Full

170

210

250

MSPS

DCS Disabled

Full

170

210

250

MSPS

CLK Period, Divide-by-1 Mode (tCLK)

Full

5.8

4.8

CLK Pulse Width High (tCH)

Divide-by-1 Mode, DCS Enabled

Full

2.61

2.9

3.19

2.16

2.4

2.64

1.8

2.0

2.2

Divide-by-1 Mode, DCS Disabled

Full

2.76

2.9

3.05

2.28

2.4

2.52

1.9

2.0

2.1

Divide-by-2 Mode Through

Divide-by-8 Mode

Full

0.8

Aperture Delay (tA)

Full

1.0

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

DATA OUTPUT PARAMETERS1

Data Propagation Delay (tPD)

Full

4.1

4.7

5.2

4.1

4.7

5.2

4.1

4.7

5.2

DCO Propagation Delay (tDCO)

Full

4.7

5.3

5.8

4.7

5.3

5.8

4.7

5.3

5.8

DCO to Data Skew (tSKEW)

Full

0.3

0.5

0.7

0.3

0.5

0.7

0.3

0.5

0.7

Pipeline Delay (Latency)

Full

Cycles

Wake-Up Time (from Standby)

Full

μs

Wake-Up Time (from Power-Down)

Full

100

μs

Out-of-Range Recovery Time

Full

Cycles

1 See

Figure 2

2 Conversion rate is the clock rate after the divider.

Timing Diagram

VIN

CLK+

CLK–

DCO–

DCO+

D0±/D1±

(LSB)

EVEN/ODD

D10±/D11±

(MSB)

N – 10

N – 9

N – 8

N – 7

N – 6

D10

N – 10

D11

N – 10

D10

N – 9

D11

N – 9

D10

N – 8

D11

N – 8

D10

N – 7

D11

N – 7

D10

N – 6

N – 1

N + 1

N + 2

N + 3

N + 4

N + 5

tCH

tPD

tSKEW

tDCO

tCLK

Figure 2. Even/Odd LVDS Mode Data Output Timing

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