ADIS16480AMLZ datasheet(6/40 Pages) AD

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ADIS16480

Data Sheet

Rev. 0 | Page 6 of 40

TIMING SPECIFICATIONS

TA = 25°C, VDD = 3.3 V, unless otherwise noted.

Table 2.

Normal Mode

Parameter

Description

Min1

Typ

Max1

Unit

fSCLK

Serial clock

0.01

MHz

tSTALL

Stall period between data

μs

tCLS

Serial clock low period

tCHS

Serial clock high period

Chip select to clock edge

tDAV

DOUT valid after SCLK edge

tDSU

DIN setup time before SCLK rising edge

tDHD

DIN hold time after SCLK rising edge

tDR, tDF

DOUT rise/fall times, ≤100 pF loading

tDSOE

CS assertion to data out active

tHD

SCLK edge to data out invalid

tDSHI

CS deassertion to data out high impedance

Input sync pulse width

μs

Input sync to data-ready output

490

μs

Input sync period

417

μs

1 Guaranteed by design and characterization, but not tested in production.

Timing Diagrams

SCLK

DOUT

DIN

R/W

MSB

DB14

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

tCS

tDSHI

tDAV

tHD

tCHS

tCLS

tDSOE

tDHD

tDSU

Figure 2. SPI Timing and Sequence

SCLK

tSTALL

Figure 3. Stall Time and Data Rate

SYNC

CLOCK (CLKIN)

DATA

READY

OUTPUT

REGISTERS

DATA VALID

Figure 4. Input Clock Timing Diagram

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