DM9106 datasheet(32/92 Pages) DAVICOM

32 / 92 page

DM9106

3-port switch with PCI Interface

Preliminary datasheet

DM9106-DS-P01

July 9, 2009

6.2.9 Reserved (CR8)

6.2.10 Management Access Register (CR9)

Bit

Name

Default

Description

31:22

RESERVED

0,RO

Reserved

LES

0,RO

Load EEPROM status

It is set to indicate the load of EEPROM is in progress.

RLM

0,RW

Reload EEPROM

Set to reload the content of EEPROM.

MDIN

0,RO

MII Management Data_In

This is a read-only bit to indicate the MDIO input data, when bit 18 MRW is set.

MRW

0,RW

MII Management Read/Write Mode Selection

This bit defines the Read/Write Mode for PHY MII management register access. 1

for read and 0 for write.

MDOUT

0,RW

MII Management Data_Out

This bit is used to generate the output data signal for PHY MII management register

access.

MDCLK

0,RW

MII Management Clock

This bit is used to generate the output clock signal for PHY MII management

RESERVED

1,RO

Reserved.

RESERVED

0,RO

Reserved.

13:12

RESERVED

0,RO

Reserved.

ERS

0,RW

EEPROM Selected

This bit is used to enable EEPROM access.

EE_TYPE

0,RO

EEPROM type

0: 93C46

1: 93C56

9:8

RESERVED

011,RW

Reserved

7:4

RESERVED

FH,RO

Reserved

CRDOUT

0,RW

Data_Out from EEPROM

This bit reflects the status of EEDI pin when the EEPROM access is enabled.

CRDIN

0,RW

Data_In to EEPROM

This bit maps to EEDO pin when the EEPROM access is enabled.

CRCLK

0,RW

Clock to EEPROM

This bit maps EECK pin when the EEPROM access is enabled

CRCS

0,RW

Chip_Select to EEPROM

This bit maps to EECS pin when the EEPROM access is enabled

DM9106 Datasheet(PDF) 32 Page - Davicom Semiconductor, Inc.

DM9106 Datasheet(HTML) 32 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL