DM9332 datasheet(23/61 Pages) DAVICOM

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DM9332

10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter

Preliminary datasheet

DM9332-15-DS-P01

March 5, 2012

6.21 Per Port VLAN Tag High Byte Register (6FH)

Bit

Name

Default

Description

7:5

PRI

PE0,RW

Tag [15:13]

CFI

PE0,RW

Tag[12]

3:0

VID118

PE0,RW

VID[11:8]

6.22 MIB counters Port Index Register (80H)

Bit

Name

Default

Description

READY

P0,RO

MIB counter data is ready

When this register is written with INDEX data, this bit is cleared and the MIB

counter reading is in progress. After end of read MIB counter, the MIB data is

loaded into register 81H~84H, and this bit is set to indicate that the MIB data is

ready.

6:5

reserved

0,RO

Reserved

4:0

INDEX

PHS0,RW MIB counter index 0~9, each counter is 32-bit in Register 81h~84h.

Write the MIB counter index to this register before read them.

6.23 MIB counter Data Register (81H~84H)

Bit

Name

Default

Description

81H

Counter0

X,RO

Counter’s data bit 7~0

82H

Counter1

X,RO

Counter’s data bit 15~8

83H

Counter2

X,RO

Counter’s data bit 23~16

84H

Counter3

X,RO

Counter’s data bit 31~24

MIB counter: RX Byte Counter Registers (INDEX 00H)

MIB counter: RX Uni-cast Packet Counter Registers (INDEX 01H)

MIB counter: RX Multi-cast Packet Counter Registers (INDEX 02H)

MIB counter: RX Discard Packet Counter Registers (INDEX 03H)

MIB counter: RX Error Packet Counter Registers (INDEX 04H)

MIB counter: TX Byte Counter Registers (INDEX 05H)

MIB counter: TX Uni-cast Packet Counter Registers (INDEX 06H)

MIB counter: TX Multi-cast Packet Counter Registers (INDEX 07H)

MIB counter: TX Discard Packet Counter Registers (INDEX 08H)

MIB counter: TX Error Packet Counter Registers (INDEX 09H)

DM9332 Datasheet(PDF) 23 Page - Davicom Semiconductor, Inc.

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