DM9332 datasheet(32/61 Pages) DAVICOM

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DM9332

10/100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter

Preliminary datasheet

DM9332-15-DS-P01

March 5, 2012

8.1 Basic Mode Control Register (BMCR) – 00H

Bit

Bit Name

Default

Description

Reset

0, RW/SC Reset

1=Software reset

0=Normal operation

This bit sets the status and controls the PHY registers to their

default states. This bit, which is self-clearing, will keep returning a

value of one until the reset process is completed

Loopback

0, RW

Loopback

Loop-back control register

1 = Loop-back enabled

0 = Normal operation

When in 100Mbps operation mode, setting this bit may cause the

descrambler to lose synchronization and produce a 720ms "dead

time" before any valid data appears at the MII receive outputs

Speed selection

1, RW

Speed Select

1 = 100Mbps

0 = 10Mbps

Link speed may be selected either by this bit or by auto-negotiation.

When auto-negotiation is enabled and bit 12 is set, this bit will return

auto-negotiation selected medium type

Auto-negotiation

enable

1, RW

Auto-negotiation Enable

1 = Auto-negotiation is enabled, bit 8 and 13 will be in

auto-negotiation status

Power down

0, RW

Power Down

While in the power-down state, the PHY should respond to

management transactions. During the transition to power-down

state and while in the power-down state, the PHY should not

generate spurious signals on the MII

1=Power down

0=Normal operation

Isolate

0,RW

Isolate

Force to 0 in application.

Restart

Auto-negotiation

0,RW/SC Restart Auto-negotiation

1 = Restart auto-negotiation. Re-initiates the auto-negotiation

process. When auto-negotiation is disabled (bit 12 of this register

cleared), this bit has no function and it should be cleared. This bit is

self-clearing and it will keep returning to a value of 1 until

auto-negotiation is initiated by the DM9332. The operation of the

auto-negotiation process will not be affected by the management

entity that clears this bit

0 = Normal operation

Duplex mode

1,RW

Duplex Mode

1 = Full duplex operation. Duplex selection is allowed when

Auto-negotiation is disabled (bit 12 of this register is cleared). With

auto-negotiation enabled, this bit reflects the duplex capability

selected by auto-negotiation

0 = Normal operation

DM9332 Datasheet(PDF) 32 Page - Davicom Semiconductor, Inc.

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