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LTC2157-14/

LTC2156-14/LTC2155-14

21576514fa

Figure 12. Functional Equivalent of Digital Output Randomizer

Figure 13. Decoding a Randomized Digital

Output Signal

APPLICATIONS INFORMATION

DATA FORMAT

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

(1.5V Range)

D13-D0

(OFFSET BINARY)

D13-D0

(2’s COMPLEMENT)

>0.75 V

+0.75V

+0.749908V

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

+0.0000915V

+0.000000V

–0.0000915V

–0.0001831V

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

–0.7499084V

–0.75V

< –0.75V

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The LSB, OF and CLKOUT out-

puts are not affected. The output randomizer is enabled

by serially programming mode control register A4.

CLKOUT

D13/D0

D12/D0

•

D1/D0

21576514 F12

D13

D12

RANDOMIZER

D13

FPGA

PC BOARD

D12

21576514 F13

D1/D0

D12/D0

D13/D0

CLKOUT

LTC2157-14

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