LT1640AL datasheet(25/34 Pages) LINER

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LTC4253/LTC4253A

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APPLICATIONS INFORMATION

VUVHI (VUV for the LTC4253A). In addition, the internal logic

checks for OV < VOVHI (VOV for the LTC4253A), RESET <

0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS and

TIMER < VTMRL. When all conditions are met, initial timing

starts and the TIMER capacitor is charged by a 5μA current

source pull-up. At time point 3, TIMER reaches the VTMRH

threshold and the initial timing cycle terminates. The TIMER

capacitor is quickly discharged. At time point 4, the VTMRL

threshold is reached and the conditions of GATE < VGATEL,

SENSE < VCB and SS < 20 • VOS must be satisfied before

the GATE start-up cycle begins. SS ramps up as dictated

by RSS • CSS; GATE is held low by the analog current

limit amplifier until SS crosses 20 • VOS. Upon releasing

GATE, 50μA sources into the external MOSFET gate and

compensation network. When the GATE voltage reaches

the MOSFET’s threshold, current begins flowing into the

load capacitor at time point 5. At time point 6, load current

reaches SS control level and the analog current limit loop

activates. Between time points 6 and 8, the GATE voltage

is servoed and the SENSE voltage is regulated at VACL(t)

and soft-start limits the slew rate of the load current. If the

SENSE voltage (VSENSE – VEE) reaches the VCB threshold

at time point 7, the circuit breaker TIMER activates. The

TIMER capacitor, CT is charged by a (200μA + 8 • IDRN)

current pull-up. As the load capacitor nears full charge,

load current begins to decline. At point 8, the load cur-

rent falls and the SENSE voltage drops below VACL(t).

The analog current limit loop shuts off and the GATE pin

ramps further. At time point 9, the SENSE voltage drops

below VCB and the fault TIMER ends, followed by a 5μA

discharge current source (cool-off). When GATE ramps

past VGATEH threshold at time point A, PWRGD1 pulls low,

starting off the PWRGD sequence. PWRGD2 pulls low at

time point C when EN2 is high and PWRGD1 is low for

more than one tSQT. PWRGD3 pulls low at time point D

when EN2 and EN3 is high and PWRGD2 is low for more

than one tSQT. At time point B, GATE reaches its maximum

voltage as determined by VIN.

Undervoltage Timing

In Figure 10 when the UV pin drops below VUVLO (VUV –

VUVHST for the LTC4253A) at time point 1, the LTC4253/

LTC4253A shut down with TIMER, SS and GATE pulled

low. If current has been flowing, the SENSE pin voltage

decreases to zero as GATE collapses. When UV recovers

and clears VUVHI (VUV for the LTC4253A) at time point 2,

an initial time cycle begins followed by a start-up cycle.

VIN Undervoltage Lockout Timing

VIN undervoltage lockout comparator, UVLO has a similar

timing behavior as the UV pin timing except it looks at

VIN < (VLKO – VLKH) to shut down and VIN > VLKO to start.

In an undervoltage lockout condition, both UV and OV

comparators are held off. When VIN exits undervoltage

lockout, the UV and OV comparators are enabled.

Overvoltage Timing

During normal operation, if the OV pin exceeds VOVHI

(VOV for the LTC4253A) as shown at time point 1 of Fig-

ure 11, the TIMER and PWRGD status are unaffected; SS

and GATE pull down; load disconnects. At time point 2,

OV recovers and drops below the VOVLO (VOV – VOVHST

for the LTC4253A) threshold; GATE start-up begins. If

the overvoltage glitch is long enough to deplete the load

capacitor, time points 4 through 7 may occur.

Circuit Breaker Timing

In Figure 12a, the TIMER capacitor charges at 200μA if

the SENSE pin exceeds VCB but VDRN is less than 5V. If

the SENSE pin returns below VCB before TIMER reaches

the VTMRH threshold, TIMER is discharged by 5μA. In

Figure 12b, when TIMER exceeds VTMRH, GATE pulls

down immediately and the chip shuts down. In Figure 12c,

multiple momentary faults cause the TIMER capacitor to

integrate and reach VTMRH followed by GATE pull down

and the chip shuts down. During chip shutdown, the

LTC4253/LTC4253A latch TIMER high with a 5μA pull-up

current source.

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