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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fd

APPLICATIONS INFORMATION

Analog Current Limit and Fast Current Limit

In Figure 17a, when SENSE exceeds VACL, GATE is

regulated by the analog current limit amplifier loop. When

SENSE drops below VACL, GATE is allowed to pull up. In

Figure 17b, when a severe fault occurs, SENSE exceeds

VFCL and GATE immediately pulls down until the analog

current amplifier establishes control. If the severe fault

causes VOUT to exceed VDRNCL, the DRAIN pin is clamped

at VDRNCL. IDRN flows into the DRAIN pin and is multiplied

by 8. This extra current is added to the TIMER pull-up

current of 230μA. This accelerated TIMER current of

[230μA+8 • IDRN] produces a shorter circuit breaker fault

delay. Careful selection of CT, RD and MOSFET can help

prevent SOA damage in a low impedance fault condition.

Soft-Start

If the SS pin is not connected, this pin defaults to a linear

voltage ramp, from 0V to 2.2V in about 180μs (or 0V to

1.4V in 230μs for the LTC4252A) at GATE start-up, as

shown in Figure 18a. If a soft-start capacitor, CSS, is con-

nected to this SS pin, the soft-start response is modified

from a linear ramp to an RC response (Equation 6), as

shown in Figure 18b. This feature allows load current to

slowly ramp-up at GATE start-up. Soft-start is initiated at

time point 3 by a TIMER transition from VTMRH to VTMRL

(time points 1 to 2) or by the OV pin falling below the

VOVLO threshold after an OV condition. When the SS pin

is below 0.2V, the analog current limit amplifier holds

GATE low. Above 0.2V, GATE is released and 58μA ramps

up the compensation network and GATE capacitance at

time point 4. Meanwhile, the SS pin voltage continues to

ramp up. When GATE reaches the MOSFET’s threshold,

the MOSFET begins to conduct. Due to the MOSFET’s high

gm, the MOSFET current quickly reaches the soft-start

control value of VACL(t) (Equation 7). At time point 6, the

GATE voltage is controlled by the current limit amplifier.

The soft-start control voltage reaches the circuit breaker

voltage, VCB, at time point 7 and the circuit breaker TIMER

activates. As the load capacitor nears full charge, load

TIMER

GATE

SENSE

VOUT

VACL

VCB

DRAIN

VTMRH

DRN

425212 F17

PWRGD

5.8μA

TIMER

GATE

SENSE

VOUT

VACL

VCB

VFCL

DRAIN

VTMRH

VDRNCL

DRN

PWRGD

CB TIMES OUT

Figure 17. Current Limit Behavior (All Waveforms Are Referenced to VEE)

(17a) Analog Current Limit Fault

(17b) Fast Current Limit Fault

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