LT4250 datasheet(8/34 Pages) LINER

8 / 34 page

LTC4253/LTC4253A

425353afe

TYPICAL PERFORMANCE CHARACTERISTICS

IPGH vs Temperature

tSS vs Temperature

tSQ vs Temperature

TEMPERATURE (°C)

–55 –35 –15

85 105 125

4253 G28

IIN = 2mA

VPWRGD = 0V

TEMPERATURE (°C)

–55 –35 –15

85 105 125

4253 G29

300

290

280

270

260

250

240

230

220

210

200

IIN = 2mA

SS PIN FLOATING

VSS RAMPS FROM 0.2V TO 2V

TEMPERATURE (°C)

–55 –35 –15

85 105 125

4253 G30

500

450

400

350

300

250

200

150

100

IIN = 2mA

VSQTMR RAMPS FROM 0.5V TO 3.5V

EN2 (Pin 1): Power Good Status Output Two Enable. This

is a TTL compatible input that is used to control PWRGD2

and PWRGD3 outputs. When EN2 is driven low, both

PWRGD2 and PWRGD3 will go high. When EN2 is driven

high, PWRGD2 will go low provided PWRGD1 has been

active for more than one power good sequence delay

(tSQT) provided by the sequencing timer. EN2 can be used

to control the power good sequence. This pin is internally

pulled low by a 120μA current source.

PWRGD2 (Pin 2): Power Good Status Output Two. Power

good sequence starts with PWRGD1 latching active low.

PWRGD2 will latch active low after EN2 goes high and

after one power good sequence delay tSQT provided by

the sequencing timer from the time PWRGD1 goes low,

whichever comes later. PWRGD2 is reset by PWRGD1

going high or EN2 going low. This pin is internally pulled

high by a 50μA current source.

PWRGD1 (Pin 3): Power Good Status Output One. At start-

up, PWRGD1 latches active low and starts the power good

sequence when the DRAIN pin is below 2.39V and GATE

is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN

(UVLO), RESET going high or circuit breaker fault time-out.

This pin is internally pulled high by a 50μA current source.

VIN (Pin 4): Positive Supply Input. Connect this pin to the

positive side of the supply through a dropping resistor. A

shunt regulator clamps VIN at 13V above VEE. An internal

undervoltage lockout (UVLO) circuit holds GATE low until

the VIN pin is greater than VLKO, overriding UV and OV. If

UV is high, OV is low and VIN comes out of UVLO, TIMER

starts an initial timing cycle before initiating GATE ramp

up. If VIN drops below approximately 8.2V (8.5V for the

LTC4253A), GATE pulls low immediately.

RESET (Pin 5): Circuit Breaker Reset Pin. This is an asyn-

chronous TTL compatible input. RESET going high will pull

GATE, SS, TIMER, SQTIMER low and the PWRGD outputs

high. The RESET pulse must be wide enough to discharge

any voltage on the TIMER pin below VTMRL. After the reset

of a latched fault, the chip waits for the interlock conditions

before recovering as described in Interlock Conditions in

the Operation section.

SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush

current during start up, thereby effecting control over di/dt.

A 20X attenuated version of the SS pin voltage is presented

to the current limit amplifier. This attenuated voltage limits

the MOSFET’s drain current through the sense resistor

during the soft-start current limiting. At the beginning of

PIN FUNCTIONS

LT4250 Datasheet(PDF) 8 Page - Linear Technology

LT4250 Datasheet(HTML) 8 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Datasheet Download

Link URL