LT4250 datasheet(28/34 Pages) LINER

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LTC4253/LTC4253A

425353afe

APPLICATIONS INFORMATION

Resetting a Fault Latch

A latched circuit breaker fault of the LTC4253/LTC4253A

has the benefit of a long cooling time. The latched fault can

be reset by pulsing the RESET pin high until the TIMER pin

is pulled below VTMRL(1V) as shown in Figure 13b. After

the RESET pulse, SS and GATE ramp up without an initial

timing cycle provided the interlock conditions are satisfied.

Alternative methods of reset include using an external

switch to pulse the UV pin below VUVLO (VUV – VUVHST

for the LTC4253A) or the VIN pin below (VLKO – VLKH).

Pulling the TIMER pin below VTMRL and the SS pin to 0V

then simultaneously releasing them also achieves a reset.

An initial timing cycle is generated for reset by pulsing the

UV pin or VIN pin, while no initial timing cycle is generated

for reset by pulsing of the TIMER and SS pins.

Using Reset as an ON/OFF Switch

The asynchronous RESET pin can be used as an ON/OFF

function to cut off supply to the external power modules

or loads controlled by the LTC4253/LTC4253A. Pulling

RESET high will pull GATE, SS, TIMER and SQTIMER

low and the PWRGD signal high. The supply is fully cut

off if the RESET pulse is maintained wide enough to fully

discharge the GATE and SS pins. As long as RESET is

high, GATE, SS, TIMER and SQTIMER are strapped to VEE

and the supply is cut off. When RESET is released, if the

LTC4253/LTC4253A are in UVLO, UV, OV or VSENSE > VCB,

turn-on is delayed until the interlock conditions are met

before recovering as described in the Operation, Interlock

Conditions section. If not, the GATE pin will ramp up in a

soft start cycle without going through an initial cycle as

in Figure 13c.

Analog Current Limit and Fast Current Limit

In Figure 14a, when SENSE exceeds VACL,GATEisregulated

by the analog current limit amplifier loop. When SENSE

drops below VACL, GATE is allowed to pull up. In Figure 14b,

when a severe fault occurs, SENSE exceeds VFCL and GATE

immediately pulls down until the analog current amplifier

establishes control. If the severe fault causes VOUTtoexceed

VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows

into the DRAIN pin and is multiplied by 8. This extra cur-

rent is added to the TIMER pull-up current of 200μA. This

accelerated TIMER current of (200μA + 8 • IDRN) produces

a shorter circuit breaker fault delay. Careful selection of

CT, RD and MOSFET helps prevent SOA damage in a low

impedance fault condition.

Soft-Start

If the SS pin is not connected, this pin defaults to a linear

voltage ramp, from 0V to 2.2V in about 300μs (0V to 1.4V

in about 200μs for the LTC4253A) at GATE start-up, as

shown in Figure 15a. If a soft-start capacitor, CSS, is con-

nected to this SS pin, the soft-start response is modified

from a linear ramp to an RC response (Equation 6), as

shown in Figure 15b. This feature allows load current to

slowly ramp-up at GATE start-up. Soft-start is initiated at

time point 3 by a TIMER transition from VTMRH to VTMRL

(time points 1 and 2), by the OV pin falling below the VOVLO

(VOV – VOVHST for the LTC4253A) threshold after an OV

condition or by the RESET pin falling < 0.8V after a Reset

condition. When the SS pin is below 0.2V, the analog cur-

rent limit amplifier keeps GATE low. Above 0.2V, GATE is

released and 50μA ramps up the compensation network

and GATE capacitance at time point 4. Meanwhile, the SS

pin voltage continues to ramp up. When GATE reaches

the MOSFET’s threshold, the MOSFET begins to conduct.

Due to the MOSFET’s high gm, the MOSFET current quickly

reaches the soft-start control value of VACL(t) (Equation 7).

At time point 6, the GATE voltage is controlled by the current

limit amplifier. The soft-start control voltage reaches the

circuit breaker voltage, VCB at time point 7 and the circuit

breaker TIMER activates. As the load capacitor nears full

charge, load current begins to decline below VACL(t). The

current limit loop shuts off and GATE releases at time

point 8. At time point 9, SENSE voltage falls below VCB

and TIMER deactivates.

Large values of CSS can cause premature circuit breaker

time-out as VACL(t)maymarginallyexceedtheVCBpotential

during the circuit breaker delay. The load capacitor is un-

able to achieve full charge in one GATE start-up cycle. A

more serious side effect of a large CSS value is that SOA

duration may be exceeded during soft-start into a low

impedance load. A soft-start voltage below VCB will not

activate the circuit breaker TIMER.

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