MK20DX32VLF5 datasheet(27/60 Pages) FREESCALE

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Table 13. MCG specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

Jacc_pll

PLL accumulated jitter over 1µs (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

1350

600

—

Dlock

Lock entry frequency tolerance

± 1.49

—

± 2.98

Dunl

Lock exit frequency tolerance

± 4.47

—

± 5.97

tpll_lock

Lock detector detection time

—

150 × 10-6

+ 1075(1/

fpll_ref)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(

Δfdco_t) over voltage and temperature should be considered.

4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

7. Excludes any oscillator currents that are also consuming power while PLL is in operation.

8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes

it is already running.

6.3.2 Oscillator electrical specifications

This section provides the electrical characteristics of the module.

6.3.2.1 Oscillator DC electrical specifications

Table 14. Oscillator DC electrical specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

VDD

Supply voltage

1.71

—

3.6

IDDOSC

Supply current — low-power mode (HGO=0)

• 32 kHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

—

500

200

300

950

1.2

1.5

—

μA

Table continues on the next page...

Peripheral operating requirements and behaviors

K20 Sub-Family Data Sheet, Rev. 4 5/2012.

Freescale Semiconductor, Inc.

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