MPC8377E datasheet(125/127 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

125

07/2011 In Section 2.2, “Power Sequencing,” updated power down sequencing information.

07/2011

• In Table 2, “Absolute Maximum Ratings1,” removed footnote 5 from LBIN to OVIN. Also, corrected

footnote 5.

•In Table 3, “Recommended Operating Conditions,” added footnote 2 to AVDD.

•In Figure 2, “Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD,” added LBVDD.

•In Table 13, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” updated IOZ min/max

to –50/50.

•In Figure 11, “RGMII and RTBI AC Timing and Multiplexing Diagrams,” added distinction between

tSKRGT_RX and tSKRGT_TX signals.

•In Table 33, “MII Management AC Timing Specifications,” updated MDC frequency—removed Min and

Max values, added Typical value. Also, updated footnote 2 and removed footnote 3.

•In Table 48, “PCI DC Electrical Characteristics,” updated VIH min value to 2.0.

•In Table 72, “TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to

be consistent with AN3665, “MPC837xE Design Checklist.”

•In Table 74, “Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,

and corrected DDR2 Minimum and Maximum Operating Frequency values.

11/2010

• In Table 25, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.

•In Table 40, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR.

•In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 23, “Clocking,” updated LCCR

to LCRR.

•In Table 72, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and

TEST_SEL1 pins—no change in functionality.

03/2010

• Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”

•In Table 34, “USB DC Electrical Characteristics,” and Table 35, “USB General Timing Parameters (ULPI

Mode Only),” added table footnotes .

•In Table 39, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 40, “Local Bus

General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.

•In Figure 22, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and

Figure 24, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted

“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.

•In Figure 63, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added

heat spreader.

•In Section 25.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list

of open drain type pins.

•In Table 72, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and

AVDD_P pins.

•in Table 72, “TePBGA II Pinout Listing,” added Note 16 to eTSEC pins.

•In Table 77, “CSB Frequency Options for Host Mode,” and Table 78, “CSB Frequency Options for Agent

Mode,” updated

csb_clk frequencies available.

•In Table 84, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”

Table 87. Document Revision History (continued)

Revision

Date

Substantive Change(s)

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