F71869AD datasheet(2/156 Pages) FINTEK

2 / 156 page

Oct., 2011

V0.19P

F71869A

F71869A Datasheet Revision History

Version

Date

Page

Revision History

0.10P

2010/04

Preliminary version

0.11P

2010/05

45, 46

47-136

1. Update CIR/CPT function description

2. Update Register

0.12P

2010/06

47, 48

65, 66

142-144

10-20

90, 91

60, 61

140

13, 21

129, 130

132

133

148

1. Modify pin54 description

2. Add scan code and OVT function description

3. Update RS485 enable register description

⎯ Index F0h

4. DC Characteristics

5. Update Pin Description

6. Update OVT register

⎯ Index 02h

7. Update Fan3 control register

⎯ Index 9Ah

8. Add Multi-Function Select Register 5

⎯ Index 2Ch

9. Correct Pin Type

10. Add Intel DSW Delay Select Register

⎯ Index FCh

11. Update STRAP_PROTECT description

12. Update Configuration Port Select Register

⎯ Index 27h

13. Add Voltage Protection Power Good Select Register

⎯ Index 3Fh

14. Add CIR Registers (CR08)

15. Update ERP PSOUT deb-register

⎯ Index E5h;

ERP S5 Delay Register

⎯ Index E7h

16. Update ERP WDT Timer

⎯ Index EEh

17. Update Application Circuit

⎯ S5# (S4#) , SUS_ACK# (3VA)

0.13P

2010/07

147

1. Update Application Circuit – Correct VIN5 pin name

0.14P

2010/08

13, 21

8, 12, 47

58~62

61, 62

122~126

135

1. Update Global Control Registers

2. Modify description for STRAP_PROTECT

3. Update GPIO for Scan Code function

4. Update GPIO Device Configuration Registers (LDN CR06)

5. Update UART IRQ Sharing Register

⎯ Index 26h bit 3

6. Update Multi-Function Select Register 1 ~ 5

⎯ Index 28h ~ 2Ch

7. Add WDT Clock Divisor High Byte

⎯ Index 29h

8. Add WDT Clock Divisor Low Byte

⎯ Index 2Ah

9. Add WDT Clock Fine Tune Count

⎯ Index 2Bh, 2Ch

10. Update GPIO 35 ~ 37 Scan Code Function Registers

11. Update ERP WDT Control register

⎯ Index EDh

0.15P

2010/08

Update for LAB version

0.16P

2010/09

12-13

12-21

131

140

121

112

139-140

150

1. Correct FDC/GPIO PWR Type

2. Correct PWR Type VCC to 3VCC

3. Add WDT Enable Register 30h and Base Address High/Low Register

60h and 61h

4. Add 2D – 2Fh in Voltage reading and limit register

5. Remove PCIRSTIN_N in VDDOK Delay Register

⎯ Index F5h bit 2

6. Correct RSTCON# pin description

7. Update GPIO4 Drive Enable Register -Index B3h bit 5~7

8. Add Auto Swap Register - Index FEh (Powered by VBAT) bit 3

9. Correct VDDOK Delay Register - Index F5h PWROK unit

10. Update Reference Circuit – Add C58

0.17P

2011/03

127

1. Made Clarification & Modification

2. Update Wakeup Control Register - Index 2Dh bit5 description

3. Add Voltage reading and limit - Index 30h, 31h

4. Modify Multi-Function Select Register 3

⎯ Index 2Ah bit 1:0

5. Modify GPIO5 KBC Emulation Control Register 2

⎯ Index AFh bit7

F71869AD Datasheet(PDF) 2 Page - Feature Integration Technology Inc.

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