864075 datasheet(19/43 Pages) INTEL

19 / 43 page

PRELIMINARY

8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

NMI

Nonmaskable Interrupt

In normal operating mode, a rising edge on NMI generates a nonmaskable

interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for

greater than one state time to guarantee that it is recognized.

ONCE

On-circuit Emulation

Holding ONCE high during the rising edge of RESET# places the device into

on-circuit emulation (ONCE) mode. This mode puts all pins into a high-imped-

ance state, thereby isolating the device from other components in the system.

The value of ONCE is latched when the RESET# pin goes inactive. While the

device is in ONCE mode, you can debug the system using a clip-on emulator.

To exit ONCE mode, reset the device by pulling the RESET# signal low. To pre-

vent accidental entry into ONCE mode, connect the ONCE pin to V

SS.

P1.7:0

I/O

Port 1

This is a standard bidirectional port that is multiplexed with individually select-

able special-function signals.

Port 1 is multiplexed as follows: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2, P1.3/EPA3,

P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.

P2.7:0

I/O

Port 2

This is a standard bidirectional port that is multiplexed with individually select-

able special-function signals.

Port 2 is multiplexed as follows: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0, P2.3/

BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT.

P3.7:0

I/O

Port 3

This is an 8-bit, bidirectional, standard I/O port.

Port 3 is multiplexed as follows: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#, P3.3/

CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3.

P4.3:0

I/O

Port 4

This is a 4-bit, bidirectional, standard I/O port with high-current drive capability.

Port 4 is multiplexed as follows: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2.

P4.3 is not multiplexed.

PLLEN2:1

Phase-locked Loop 1 and 2 Enable

These input pins are used to enable the on-chip clock multiplier feature and

select either the doubled or quadrupled clock speed as follows:

PLLEN2

PLLEN1

Mode

Standard mode; clock multiplier circuitry disabled.

Internal clock equals the XTAL1 input frequency.

Reserved†

Doubled mode; clock multiplier circuitry enabled.

Internal clock is twice the XTAL1 input frequency.

Quadrupled mode; clock multiplier circuitry enabled.

Internal clock is four times the XTAL1 input

frequency.

† This reserved combination causes the device to enter an unsupported test

mode.

Table 8. Signal Descriptions (Continued)

Name

Type

Description

864075 Datasheet(PDF) 19 Page - Intel Corporation

864075 Datasheet(HTML) 19 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL