DA[9:0]

DB[9:0]

SLEEP

CLKA/B

WRTA/B

Internal

DigitalIn

DVDD

400W

100kW

DGND

GSET

MODE

Internal

DigitalIn

DVDD

400W

100kW

DGND

DAC5652

SLAS452C – MARCH 2005 – REVISED DECEMBER 2010

www.ti.com

Digital Inputs and Timing

Digital Inputs

The data input ports of the DAC5652 accept a standard positive coding with data bits DA9 and DB9 being the

most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best

performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may

vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their

specified limits.

equivalent CMOS digital inputs of the DAC5652. The pullup and pulldown circuitry is approximately equivalent to

100k

Ω.The 10-bit digital data input follows the offset positive binary coding scheme. The DAC5652 is designed to

operate with a digital supply (DVDD) of 3 V to 3.6 V.

Figure 13. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor

Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor

12

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