DA[9:0]/DB[9:0]

WRTA/WRTB

CLKA/CLKB

IOUT

or

IOUT

Valid Data

DAC5652

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SLAS452C – MARCH 2005 – REVISED DECEMBER 2010

Input Interfaces

•

For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own

separate data input bus, clock input, and data write signal (data latch-in).

•

In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The

B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.

Table 1. Operating Modes

MODE Pin

MODE pin connected to DGND

MODE pin connected to DVDD

Bus input

Single-bus interleaved mode, clock and write input equal for both DACs

Dual-bus mode, DACs operate independently

Dual-Bus Data Interface and Timing

In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5652 consist

of two independent, 10-bit, parallel data ports. Each DAC channel is controlled by its own set of write (WRTA,

WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the CLKA/B lines

control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRTA/B line.

The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock

domains having equal periods (but possibly different phases) are input to the DAC5652. This is defined by a

minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.

This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of

the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the

rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected

externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.

Figure 15. Dual-Bus Mode Operation

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