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AM3703 Datasheet(PDF) 45 Page - Texas Instruments

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Part # AM3703
Description  AM3715, AM3703 Sitara ARM Microprocessors
PDF  280 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3703 Datasheet(HTML) 45 Page - Texas Instruments

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AM3715, AM3703
www.ti.com
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
Reference Manual (literature number SPRUGN4).
(13) In the safe_mode_out1, the buffer is configured to drive 1.
(14) Mux0 if sys_boot6 is pulled down (clock master).
(15) If MMC1 functional signals are enabled, vdds_mmc1 for MMC1 must be supplied by a dedicated power source.
If MMC1 functional signals are disabled, other multiplexed CMOS signals of the interface can be enabled. The interface can be supplied
by the same power source as vdds. The vdds power source supplies the vdds_mmc1 ball.
If neither MMC1 functional balls or CMOS signals are enabled, the interface balls are left unconnected with its associated power supply
(vdda/vssa) grounded.
For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model /
Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
Table 2-2. Ball Characteristics (CBC Pkg.)(5)
BALL
BALL TOP
PIN NAME [2]
MODE [3]
TYPE [4]
BALL
BALL RESET RESET
POWER [8] HYS [9]
BUFFER
PULLUP
IO CELL
BOTTOM
[1]
RESET
REL. STATE
REL. MODE
STRENGTH /DOWN
[12]
[1]
STATE [5]
[6]
[7]
(mA) [10]
TYPE [11]
AE16
NA
cam_d0
0
I
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
gpio_99
4
I
safe_mode
7
-
AE15
NA
cam_d1
0
I
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
gpio_100
4
I
safe_mode
7
-
AD17
NA
gpio_112
4
I
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
safe_mode
7
-
AE18
NA
gpio_114
4
I
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
safe_mode
7
-
AD16
NA
gpio_113
4
I
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
safe_mode
7
-
gpio_115
4
I
AE17
NA
safe_mode
7
-
L
L
7
vdda
Yes
NA
PU/ PD
LVCMOS
NA
G20
sdrc_a0
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
K20
sdrc_a1
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
J20
sdrc_a2
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
J21
sdrc_a3
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
U21
sdrc_a4
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
R20
sdrc_a5
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
M21
sdrc_a6
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
M20
sdrc_a7
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
N20
sdrc_a8
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
K21
sdrc_a9
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
Y16
sdrc_a10
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
N21
sdrc_a11
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
R21
sdrc_a12
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
AA15
sdrc_a13
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
Y12
sdrc_a14
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
AA18
sdrc_ba0
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
V20
sdrc_ba1
0
O
0
0
0
vdds
NA
4
(1)
PU/ PD
LVCMOS
NA
Y15
sdrc_cke0
0
O
H
1
7
vdds
NA
4
(1)
PU/ PD
LVCMOS
safe_mode_out1
(6)
7
NA
Y13
sdrc_cke1
0
O
H
1
7
vdds
NA
4
(1)
PU/ PD
LVCMOS
safe_mode_out1
(6)
7
NA
A12
sdrc_clk
0
IO
L
0
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
D1
sdrc_d0
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
G1
sdrc_d1
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
G2
sdrc_d2
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
E1
sdrc_d3
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
D2
sdrc_d4
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
E2
sdrc_d5
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
NA
B3
sdrc_d6
0
IO
L
Z
0
vdds
Yes
4
(1)
PU/ PD
LVCMOS
Copyright
© 2010–2011, Texas Instruments Incorporated
TERMINAL DESCRIPTION
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