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AM3703 Datasheet(PDF) 50 Page - Texas Instruments

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Part # AM3703
Description  AM3715, AM3703 Sitara ARM Microprocessors
PDF  280 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

AM3703 Datasheet(HTML) 50 Page - Texas Instruments

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AM3715, AM3703
SPRS616F
– JUNE 2010 – REVISED AUGUST 2011
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(5) (continued)
BALL
BALL TOP
PIN NAME [2]
MODE [3]
TYPE [4]
BALL
BALL RESET RESET
POWER [8] HYS [9]
BUFFER
PULLUP
IO CELL
BOTTOM
[1]
RESET
REL. STATE
REL. MODE
STRENGTH /DOWN
[12]
[1]
STATE [5]
[6]
[7]
(mA) [10]
TYPE [11]
sys_ndmareq1
1
I
uart4_rx
2
I
gpio_65
4
IO
safe_mode
7
-
W19
NA
hsusb0_clk
0
I
L
L
7
vdds
Yes
8
PU/ PD
LVCMOS
gpio_120
4
IO
safe_mode
7
-
V20
NA
hsusb0_data0
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart3_tx_irtx
2
O
gpio_125
4
IO
uart2_tx
5
O
safe_mode
7
-
Y20
NA
hsusb0_data1
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart3_rx_irrx
2
I
gpio_130
4
IO
uart2_rx
5
I
safe_mode
7
-
V18
NA
hsusb0_data2
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart3_rts_sd
2
O
gpio_131
4
IO
uart2_rts
5
O
safe_mode
7
-
W20
NA
hsusb0_data3
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
uart3_cts_rctx
2
IO
gpio_169
4
IO
uart2_cts
5
I
safe_mode
7
-
W17
NA
hsusb0_data4
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_188
4
IO
safe_mode
7
-
Y18
NA
hsusb0_data5
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_189
4
IO
safe_mode
7
-
Y19
NA
hsusb0_data6
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_190
4
IO
safe_mode
7
-
Y17
NA
hsusb0_data7
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_191
4
IO
safe_mode
7
-
V19
NA
hsusb0_dir
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_122
4
IO
safe_mode
7
-
W18
NA
hsusb0_nxt
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_124
4
IO
safe_mode
7
-
U20
NA
hsusb0_stp
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_121
4
IO
safe_mode
7
-
U15
NA
jtag_ntrst
0
I
L
L
0
vdds
Yes
NA
PU/ PD
LVCMOS
W13
NA
jtag_rtck
0
O
L
0
0
vdds
NA
4
PU/ PD
LVCMOS
V14
NA
jtag_tck
0
I
L
L
0
vdds
Yes
NA
PU/ PD
LVCMOS
U16
NA
jtag_tdi
0
I
H
H
0
vdds
Yes
NA
PU/ PD
LVCMOS
Y13
NA
jtag_tdo
0
O
L
Z
0
vdds
NA
4
PU/ PD
LVCMOS
V15
NA
jtag_tms_tmsc
0
IO
H
H
0
vdds
Yes
4
PU/ PD
LVCMOS
50
TERMINAL DESCRIPTION
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