DAC5674

SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005

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The external loop filter components C1, C2, and R1 are given by choosing Gvco, N = Fvco/Fdata, the loop

phase margin

require a fast PLL lock time, it is suggested that

suppression of the phase noise side lobes. Phase margins of 60 degrees or less have occasionally been

sensitive to board layout and decoupling details.

The optimum loop bandwidth

and the application. For the foregoing example with Gvco = 210 MHz/V, an

lower and higher loop bandwidths may provide better phase-noise characteristics. For a higher Gvco, for

example Gvco = 400 MHz/V, a

experiment with varying the loop bandwidth by at least 1/2

× through 2× to verify the optimum setting.

C1, C2, and R1 are then calculated by the following equations:

C1

+ t1 1– t2

t3

C2

+ t1–t2

t3

R1

+

t1(t3 * t2)

where

t1 +

K

d

tan

f

t2 +

1

w

t3 +

tan

f

w

d

and

charge pump current

:

iqp = 1 mA

vco gain:

Kvco = 2

π × Gvco rad/V

Fvco/Fdata:

N = {2, 4, 8, 16, 32}

phase detector gain:

Kd = iqp

An Excel

 spreadsheet is provided by TI for automatically calculating the values for C1, C2, and R.

Completing the preceding example with

PARAMETER

VALUE

UNIT

Gvco

2.10E+02

MHz/V

1.00E+00

MHz

N

4

80

degrees

the component values are

C1 (F)

C2 (F)

R (

W)

1.51E−08

1.16E−10

1.21E+02

As the PLL characteristics are not sensitive to these components, the closest 20% tolerance capacitor and 1%

tolerance resistor values can be used. If the calculation results in a negative value for C2 or an unrealistically

large value for C1, then the phase margin may need to be reduced slightly.

USING PowerPAD DEVICES

A thermal land should be placed on the top and bottom layers of the circuit board. The recommended thermal

land size for this package is 5 mm

× 5 mm, with top and bottom layers connected by 9 vias. A thermal land size

of 3,8 mm

× 3,8 mm (as used on the DAC5674 EVM) is adequate for this device.