COP888CL datasheet(21/42 Pages) TI1

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Power Save Modes (Continued)

introduced or not. The delay is included if CLKDLY is set,

and excluded if CLKDLY is reset. The CLKDLY bit is cleared

on reset.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a “1” to the HALT flag will have no

effect).

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit, if enabled,

remains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

IDLE MODE

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activity, except the

associated on-board oscillator circuitry, the WATCHDOG

logic, the clock monitor and the IDLE Timer T0, is stopped.

As with the HALT mode, the device can be returned to

normal operation with a reset, or with a Multi-Input Wake-up

from the L Port. Alternately, the microcontroller resumes

normal operation from the IDLE mode when the thirteenth bit

(representing 4.096 ms at internal clock frequency of 1 MHz,

c = 1 µs) of the IDLE Timer toggles.

This toggle condition of the thirteenth bit of the IDLE Timer

T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the thirteenth bit of the IDLE Timer T0. The interrupt can

be enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

Multi-Input Wakeup

The Multi-Input Wakeup feature is used to return (wakeup)

the device from either the HALT or IDLE modes. Alternately

Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 8 edge selectable external interrupts.

Figure 11 shows the Multi-Input Wakeup logic.

The Multi-Input Wakeup feature utilizes the L Port. The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes.

The selection is done through the Reg: WKEN. The Reg:

WKEN is an 8-bit read/write register, which contains a con-

trol bit for every L port bit. Setting a particular WKEN bit

enables a Wakeup from the associated L port pin.

The user can select whether the trigger condition on the

selected L Port pin is going to be either a positive edge (low

to high transition) or a negative edge (high to low transition).

This selection is made via the Reg: WKEDG, which is an

8-bit control register with a bit assigned to each L Port pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

RBIT

5, WKEN

SBIT

5, WKEDG

RBIT

5, WKPND

SBIT

5, WKEN

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected L port bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the associated WKPND bits being cleared.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the

corresponding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user has the

responsibility of clearing the pending flags before attempting

to enter the HALT mode.

The WKEN, WKPND and WKEDG are all read/write regis-

ters, and are cleared at reset.

COP888CL Datasheet(PDF) 21 Page - Texas Instruments

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